From patchwork Sun Apr 23 09:17:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: igall@marvell.com X-Patchwork-Id: 754513 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wBhdM02RTz9s85 for ; Tue, 25 Apr 2017 09:00:22 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9A5B2C21C8C; Mon, 24 Apr 2017 22:58:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 697B3C21C5A; Mon, 24 Apr 2017 22:58:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 388B6C21C1F; Sun, 23 Apr 2017 09:19:18 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lists.denx.de (Postfix) with ESMTPS id 81B46C21C1F for ; Sun, 23 Apr 2017 09:19:17 +0000 (UTC) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v3N9FHVj029273; Sun, 23 Apr 2017 02:19:12 -0700 Received: from il-exch01.marvell.com ([199.203.130.101]) by mx0b-0016f401.pphosted.com with ESMTP id 2a06pfjy3w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Apr 2017 02:19:12 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by IL-EXCH01.marvell.com (10.4.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Sun, 23 Apr 2017 12:19:09 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Sun, 23 Apr 2017 02:19:09 -0700 Received: from igall-OptiPlex-990.pt.marvell.com (unknown [10.5.24.64]) by maili.marvell.com (Postfix) with ESMTP id C7CC23F7040; Sun, 23 Apr 2017 02:19:07 -0700 (PDT) From: To: Date: Sun, 23 Apr 2017 12:17:25 +0300 Message-ID: <1492939057-4724-2-git-send-email-igall@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492939057-4724-1-git-send-email-igall@marvell.com> References: <1492939057-4724-1-git-send-email-igall@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-23_08:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1704230165 X-Mailman-Approved-At: Mon, 24 Apr 2017 22:58:32 +0000 Cc: nadavh@marvell.com, sr@denx.de, neta@marvell.com, Igal Liberman Subject: [U-Boot] [PATCH 01/13] phy: marvell: comphy: Replace PHY_TYPE_KR with PHY_TYPE_SFI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Roese Use correct naming as done in the latest Marvell U-Boot version as well. Change-Id: Ic65c74b709e0c5c262673d840fdc22351d6aeabf Signed-off-by: Stefan Roese Signed-off-by: Igal Liberman --- arch/arm/dts/armada-8040-db.dts | 8 ++++---- arch/arm/dts/armada-8040-mcbin.dts | 10 +++++----- drivers/phy/marvell/comphy_core.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 18 +++++++++--------- include/dt-bindings/comphy/comphy_data.h | 2 +- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index f1f196f..76fd004 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -205,7 +205,7 @@ * Serdes Configuration: * Lane 0: SGMII2 * Lane 1: USB3_HOST0 - * Lane 2: KR (10G) + * Lane 2: SFI (10G) * Lane 3: SATA1 * Lane 4: USB3_HOST1 * Lane 5: PEX2x1 @@ -220,7 +220,7 @@ }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { @@ -241,7 +241,7 @@ * Serdes Configuration: * Lane 0: SGMII2 * Lane 1: USB3_HOST0 - * Lane 2: KR (10G) + * Lane 2: SFI (10G) * Lane 3: SATA1 * Lane 4: Unconnected * Lane 5: PEX2x1 @@ -256,7 +256,7 @@ }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index e42b092..dde495a 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -99,7 +99,7 @@ * [54] 2.5G SFP LOS * [55] Micro SD card detect * [56-61] Micro SD - * [62] CP1 KR SFP FAULT + * [62] CP1 SFI SFP FAULT */ /* 0 1 2 3 4 5 6 7 8 9 */ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff @@ -163,7 +163,7 @@ * Lane 1: PCIe0 (x4) * Lane 2: PCIe0 (x4) * Lane 3: PCIe0 (x4) - * Lane 4: KR (10G) + * Lane 4: SFI (10G) * Lane 5: SATA1 */ phy0 { @@ -179,7 +179,7 @@ phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; @@ -268,7 +268,7 @@ * Lane 1: SATA 0 * Lane 2: USB HOST 0 * Lane 3: SATA1 - * Lane 4: KR (10G) + * Lane 4: SFI (10G) * Lane 5: SGMII3 */ phy0 { @@ -285,7 +285,7 @@ phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index caa1928..ac084a6 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -37,7 +37,7 @@ static char *get_type_string(u32 type) "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "KR"}; + "RXAUI0", "RXAUI1", "SFI"}; if (type < 0 || type > PHY_TYPE_MAX) return "invalid"; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 25c067d..cd3cf96 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -34,7 +34,7 @@ struct utmi_phy_data { * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet * option has different options, for example: serdes lane2 had option - * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR) + * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ @@ -43,13 +43,13 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_XAUI1, 0x1}, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, @@ -907,8 +907,8 @@ static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, return ret; } -static int comphy_kr_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) +static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, + void __iomem *comphy_base) { u32 mask, data, ret = 1; void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); @@ -1696,9 +1696,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, lane, ptr_comphy_map->speed, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_KR: - ret = comphy_kr_power_up(lane, hpipe_base_addr, - comphy_base_addr); + case PHY_TYPE_SFI: + ret = comphy_sfi_power_up(lane, hpipe_base_addr, + comphy_base_addr); break; case PHY_TYPE_RXAUI0: case PHY_TYPE_RXAUI1: diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index a3a6b40..8fd578a 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -42,7 +42,7 @@ #define PHY_TYPE_XAUI3 20 #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_KR 23 +#define PHY_TYPE_SFI 23 #define PHY_TYPE_MAX 24 #define PHY_TYPE_INVALID 0xff