From patchwork Thu Apr 20 08:15:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 752699 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w7sBp1LQ8z9s2x for ; Thu, 20 Apr 2017 18:16:02 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="uausJO3R"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id CA834C21D86; Thu, 20 Apr 2017 08:15:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4322C21C76; Thu, 20 Apr 2017 08:15:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 770B3C21C76; Thu, 20 Apr 2017 08:15:45 +0000 (UTC) Received: from mail-yb0-f193.google.com (mail-yb0-f193.google.com [209.85.213.193]) by lists.denx.de (Postfix) with ESMTPS id DCDCAC21C50 for ; Thu, 20 Apr 2017 08:15:44 +0000 (UTC) Received: by mail-yb0-f193.google.com with SMTP id l192so2692468ybl.1 for ; Thu, 20 Apr 2017 01:15:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=sGpl2a/22W9qDDuc3xb44R0AJTxZ+ArXNEqzZLDEbUo=; b=uausJO3R/kgegmKbR87gCwpXyCyrpOkJkXOcSWwlKYEJ0XiSswa02wNqppmKQEQAAQ n08Jb8fxrc5cfyiEtv/2Ba0fOu/XOC2o+aapR3vz61wQ9hD4SfOPJbN4ZoKN6myoOL52 V9nukI8WeOqT36CkPagztc902JWwKsXDHUjbX3DQFYbwvV0Izlu4fBvgT9f+3BJWTmFx H+ZTMkwV6H4CmEYVFt45Bik6XkCfPi8N7NJnmD0MSFLHrIqMod+iqc7b9VHlonULmJHn i4DNMb/wbC2PJ9ofV5USAW3xjMgTsu6sv8x+eMRLHb0E3b/t9TbF+KeyhrmnB66wLgLk lpHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=sGpl2a/22W9qDDuc3xb44R0AJTxZ+ArXNEqzZLDEbUo=; b=UF/kRccVgUm29vVX+gRP8EzIxiEuREA1NhRHHsRv0kCrksVOzy70A8AKA7bTX6PK10 hA244gkhinqTHp4yW8vVU7NSWvw8c2Ef6R0cs9fUVtYBDUPW8cbqtCXB4W+EnyIJS4nx Cc3jrKSMCrL3pZ4KssLWcZ2s9Ku4cDaJBHIrBulIvZaPisUhs1VRQfhbujOHjhmPcK3W 67SmfwNE2rdCBSLAwfNBj+KJMgd32mvr7jn3FZnoXomTqZvRAtJda0xkOaFyLKJldeAq wiicUsI+B5FjqQQZXxbIdJ0Q9OEGKpNwuoxZUirE20+8vJqww5dWyZbKKCedAVUpOmcq m9tA== X-Gm-Message-State: AN3rC/4OaMqjADIgjwpCiwbsBfo/fa4KcpwvKOmwYQq/s7D8I91HFKiU zWgkAnXcTyTXrA== X-Received: by 10.98.134.194 with SMTP id x185mr6797426pfd.106.1492676143511; Thu, 20 Apr 2017 01:15:43 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id b128sm8762561pgc.16.2017.04.20.01.15.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Apr 2017 01:15:42 -0700 (PDT) From: Kever Yang To: sjg@chromium.org Date: Thu, 20 Apr 2017 16:15:34 +0800 Message-Id: <1492676134-21452-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 Cc: Lin huang , u-boot@lists.denx.de, Joe Hershberger , Philipp Tomsich Subject: [U-Boot] [PATCH] rockchip: pinctrl: rk3399: add gmac io strength support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" GMAC controller need to init the tx io driver strength to 13mA, just like the description in dts pinctrl node, or else the controller may only work in 100MHz Mode, and fail to work at 1000MHz mode. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich > Reviewed-by: Simon Glass Reviewed-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 75 +++++++++++++++++++++++-- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 18 ++++++ 2 files changed, 89 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index b340b05..e8a6f71 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -151,10 +151,11 @@ struct rk3399_grf_regs { u32 gpio2_sr[3][4]; u32 reserved23[4]; u32 gpio2_smt[3][4]; - u32 reserved24[(0xe130 - 0xe0ec)/4 - 1]; - u32 gpio4b_e01; - u32 gpio4b_e2; - u32 reserved24a[(0xe200 - 0xe134)/4 - 1]; + u32 reserved24[(0xe100 - 0xe0ec)/4 - 1]; + u32 gpio2_e[4]; + u32 gpio3_e[7]; + u32 gpio4_e[5]; + u32 reserved24a[(0xe200 - 0xe13c)/4 - 1]; u32 soc_con0; u32 soc_con1; u32 soc_con2; @@ -435,6 +436,72 @@ enum { GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, GRF_PWM_1 = 1, + /* GRF_GPIO3A_E01 */ + GRF_GPIO3A0_E_SHIFT = 0, + GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT, + GRF_GPIO3A1_E_SHIFT = 3, + GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT, + GRF_GPIO3A2_E_SHIFT = 6, + GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT, + GRF_GPIO3A3_E_SHIFT = 9, + GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT, + GRF_GPIO3A4_E_SHIFT = 12, + GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT, + GRF_GPIO3A5_E0_SHIFT = 15, + GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT, + + /* GRF_GPIO3A_E2 */ + GRF_GPIO3A5_E12_SHIFT = 0, + GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT, + GRF_GPIO3A6_E_SHIFT = 2, + GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT, + GRF_GPIO3A7_E_SHIFT = 5, + GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT, + + /* GRF_GPIO3B_E01 */ + GRF_GPIO3B0_E_SHIFT = 0, + GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT, + GRF_GPIO3B1_E_SHIFT = 3, + GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT, + GRF_GPIO3B2_E_SHIFT = 6, + GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT, + GRF_GPIO3B3_E_SHIFT = 9, + GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT, + GRF_GPIO3B4_E_SHIFT = 12, + GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT, + GRF_GPIO3B5_E0_SHIFT = 15, + GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT, + + /* GRF_GPIO3A_E2 */ + GRF_GPIO3B5_E12_SHIFT = 0, + GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT, + GRF_GPIO3B6_E_SHIFT = 2, + GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT, + GRF_GPIO3B7_E_SHIFT = 5, + GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT, + + /* GRF_GPIO3C_E01 */ + GRF_GPIO3C0_E_SHIFT = 0, + GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT, + GRF_GPIO3C1_E_SHIFT = 3, + GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT, + GRF_GPIO3C2_E_SHIFT = 6, + GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT, + GRF_GPIO3C3_E_SHIFT = 9, + GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT, + GRF_GPIO3C4_E_SHIFT = 12, + GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT, + GRF_GPIO3C5_E0_SHIFT = 15, + GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT, + + /* GRF_GPIO3C_E2 */ + GRF_GPIO3C5_E12_SHIFT = 0, + GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT, + GRF_GPIO3C6_E_SHIFT = 2, + GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT, + GRF_GPIO3C7_E_SHIFT = 5, + GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT, + /* GRF_SOC_CON7 */ GRF_UART_DBG_SEL_SHIFT = 10, GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index 507bec4..6b62a0c 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -232,6 +232,24 @@ static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) rk_clrsetreg(&grf->gpio3c_iomux, GRF_GPIO3C1_SEL_MASK, GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); + + /* Set drive strength for GMAC tx io, value 3 means 13mA */ + rk_clrsetreg(&grf->gpio3_e[0], + GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK | + GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK, + 3 << GRF_GPIO3A0_E_SHIFT | + 3 << GRF_GPIO3A1_E_SHIFT | + 3 << GRF_GPIO3A4_E_SHIFT | + 1 << GRF_GPIO3A5_E0_SHIFT); + rk_clrsetreg(&grf->gpio3_e[1], + GRF_GPIO3A5_E12_MASK, + 1 << GRF_GPIO3A5_E12_SHIFT); + rk_clrsetreg(&grf->gpio3_e[2], + GRF_GPIO3B4_E_MASK, + 3 << GRF_GPIO3B4_E_SHIFT); + rk_clrsetreg(&grf->gpio3_e[4], + GRF_GPIO3C1_E_MASK, + 3 << GRF_GPIO3C1_E_SHIFT); } #endif