From patchwork Thu Apr 20 04:45:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: eric.gao@rock-chips.com X-Patchwork-Id: 752640 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w7mhM0Sl3z9s0g for ; Thu, 20 Apr 2017 14:52:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C5E0EC21DB6; Thu, 20 Apr 2017 04:49:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3F81FC21D96; Thu, 20 Apr 2017 04:48:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7CCF5C21CFF; Thu, 20 Apr 2017 04:48:02 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.133]) by lists.denx.de (Postfix) with ESMTPS id 50B4FC21D76 for ; Thu, 20 Apr 2017 04:47:55 +0000 (UTC) Received: from eric.gao?rock-chips.com (unknown [192.168.165.141]) by regular1.263xmail.com (Postfix) with ESMTP id 6EA008F21; Thu, 20 Apr 2017 12:47:47 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from smtp.263.net (sg-smtp01.263.net [54.255.195.220]) by smtp.263.net (Postfix) with ESMTP id 3680D424; Thu, 20 Apr 2017 12:47:46 +0800 (CST) Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 97B8FDF30F; Thu, 20 Apr 2017 12:47:46 +0800 (CST) X-RL-SENDER: eric.gao@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: eric.gao@rock-chips.com X-UNIQUE-TAG: <666760a1189d264cb9d6df30037371cd> X-ATTACHMENT-NUM: 0 X-SENDER: eric.gao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith ESMTP id 8953OLMUL; Thu, 20 Apr 2017 12:47:47 +0800 (CST) From: Eric Gao To: sjg@chromium.org Date: Thu, 20 Apr 2017 12:45:58 +0800 Message-Id: <1492663559-8248-11-git-send-email-eric.gao@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492663559-8248-1-git-send-email-eric.gao@rock-chips.com> References: <1492663559-8248-1-git-send-email-eric.gao@rock-chips.com> Cc: u-boot@lists.denx.de, eric.gao@rock-chips.com, Philipp Tomsich , MengDongyang Subject: [U-Boot] [PATCH v4 10/11] rockchip: dts: Add mipi dsi support for rk3399 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add dts config for mipi display, include vop, mipi controller, panel, backlight . And Enable rk808 for lcd_3v3 in another patch. Signed-off-by: Eric Gao Acked-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: -Add dts config for mipi display. arch/arm/dts/rk3399-evb.dts | 84 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/rk3399.dtsi | 72 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 156 insertions(+) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index e1f867b..3d6f3ce 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -59,6 +59,15 @@ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; }; + backlight: backlight { + compatible = "pwm-backlight"; + status = "disabled"; + }; + + panel:panel { + compatible = "simple-panel"; + status = "disabled"; + }; }; &emmc_phy { @@ -141,6 +150,7 @@ status = "okay"; vcc12-supply = <&vcc3v3_sys>; + regulators { vcc33_lcd: SWITCH_REG2 { regulator-always-on; @@ -151,6 +161,80 @@ }; }; +&backlight { + power-supply = <&vccsys>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + pwm-delay-us = <10000>; + status = "okay"; + }; + +&panel { + power-supply = <&vcc33_lcd>; + backlight = <&backlight>; + /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/ + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + rockchip,panel = <&panel>; + display-timings { + timing0 { + bits-per-pixel = <24>; + clock-frequency = <160000000>; + hfront-porch = <120>; + hsync-len = <20>; + hback-porch = <21>; + hactive = <1200>; + vfront-porch = <21>; + vsync-len = <3>; + vback-porch = <18>; + vactive = <1920>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; +}; + &pinctrl { pmic { pmic_int_l: pmic-int-l { diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index d94d780..9344a43 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -684,6 +684,78 @@ status = "disabled"; }; + vopl: vop@ff8f0000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-vop-lit"; + reg = <0x0 0xff8f0000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; + reset-names = "axi", "ahb", "dclk"; + status = "okay"; + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopl_out_mipi: endpoint@0 { + reg = <3>; + remote-endpoint = <&mipi_in_vopl>; + }; + }; + }; + + vopb: vop@ff900000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-vop-big"; + reg = <0x0 0xff900000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + #clock-cells = <0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; + reset-names = "axi", "ahb", "dclk"; + /*power-domains = <&power RK3399_PD_VOPB>;*/ + status = "okay"; + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopb_out_mipi: endpoint@0 { + reg = <3>; + remote-endpoint = <&mipi_in_vopb>; + }; + }; + }; + + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3399_mipi_dsi"; + reg = <0x0 0xff960000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>; + clock-names = "ref", "pclk", "phy_cfg"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + pinctrl: pinctrl { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl";