From patchwork Sun Apr 16 09:44:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Ziyuan X-Patchwork-Id: 751126 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w5RQW022zz9s4s for ; Sun, 16 Apr 2017 19:47:46 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id AC554C21C40; Sun, 16 Apr 2017 09:46:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 701A3C21C4D; Sun, 16 Apr 2017 09:46:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 48A7FC21C45; Sun, 16 Apr 2017 09:45:55 +0000 (UTC) Received: from regular2.263xmail.com (regular2.263xmail.com [211.157.152.3]) by lists.denx.de (Postfix) with ESMTPS id 3F8D3C21C4C for ; Sun, 16 Apr 2017 09:45:48 +0000 (UTC) Received: from regular1.263xmail.com (unknown [192.168.165.111]) by regular2.263xmail.com (Postfix) with ESMTP id ADB791E8DD for ; Sun, 16 Apr 2017 17:45:38 +0800 (CST) Received: from xzy.xu?rock-chips.com (unknown [192.168.167.227]) by regular1.263xmail.com (Postfix) with ESMTP id 3107446; Sun, 16 Apr 2017 17:45:19 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id D9080360; Sun, 16 Apr 2017 17:45:18 +0800 (CST) X-RL-SENDER: xzy.xu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 220.200.42.25 X-LOGIN-NAME: xzy.xu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: xzy.xu@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [220.200.42.25]) by smtp.263.net (Postfix) whith SMTP id 5990A2TTR8; Sun, 16 Apr 2017 17:45:19 +0800 (CST) From: Ziyuan Xu To: u-boot@lists.denx.de Date: Sun, 16 Apr 2017 17:44:45 +0800 Message-Id: <1492335886-1776-4-git-send-email-xzy.xu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492335886-1776-1-git-send-email-xzy.xu@rock-chips.com> References: <1492335886-1776-1-git-send-email-xzy.xu@rock-chips.com> Cc: Stephen Warren , Lin huang Subject: [U-Boot] [PATCH 4/5] rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: Ziyuan Xu Acked-by: Simon Glass --- drivers/clk/rockchip/clk_rk3288.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 7835676..fc369dd 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -513,16 +513,19 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case HCLK_EMMC: + case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; break; case HCLK_SDMMC: + case SCLK_SDMMC: con = readl(&cru->cru_clksel_con[11]); mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; break; case HCLK_SDIO0: + case SCLK_SDIO0: con = readl(&cru->cru_clksel_con[12]); mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; @@ -556,6 +559,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, } switch (periph) { case HCLK_EMMC: + case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], EMMC_PLL_MASK << EMMC_PLL_SHIFT | EMMC_DIV_MASK << EMMC_DIV_SHIFT, @@ -563,6 +567,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDMMC: + case SCLK_SDMMC: rk_clrsetreg(&cru->cru_clksel_con[11], MMC0_PLL_MASK << MMC0_PLL_SHIFT | MMC0_DIV_MASK << MMC0_DIV_SHIFT, @@ -570,6 +575,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, (src_clk_div - 1) << MMC0_DIV_SHIFT); break; case HCLK_SDIO0: + case SCLK_SDIO0: rk_clrsetreg(&cru->cru_clksel_con[12], SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, @@ -662,6 +668,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk) case HCLK_EMMC: case HCLK_SDMMC: case HCLK_SDIO0: + case SCLK_EMMC: + case SCLK_SDMMC: + case SCLK_SDIO0: new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); break; case SCLK_SPI0: @@ -706,6 +715,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) case HCLK_EMMC: case HCLK_SDMMC: case HCLK_SDIO0: + case SCLK_EMMC: + case SCLK_SDMMC: + case SCLK_SDIO0: new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); break; case SCLK_SPI0: