From patchwork Tue Mar 28 15:36:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kostya Porotchkin X-Patchwork-Id: 744367 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vsw280fwXz9s2s for ; Wed, 29 Mar 2017 02:35:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 9604FC21C35; Tue, 28 Mar 2017 15:34:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8D9ECC21C45; Tue, 28 Mar 2017 15:34:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 98C55C21C36; Tue, 28 Mar 2017 15:33:57 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lists.denx.de (Postfix) with ESMTPS id C36BCC21C30 for ; Tue, 28 Mar 2017 15:33:52 +0000 (UTC) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2SFPPi6027181; Tue, 28 Mar 2017 08:33:49 -0700 Received: from il-exch01.marvell.com ([199.203.130.101]) by mx0a-0016f401.pphosted.com with ESMTP id 29fqpqry9w-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 28 Mar 2017 08:33:48 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by IL-EXCH01.marvell.com (10.4.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 28 Mar 2017 18:33:44 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 28 Mar 2017 08:33:43 -0700 Received: from Malogato.pt.marvell.com (unknown [10.5.24.37]) by maili.marvell.com (Postfix) with ESMTP id 4AD623F7044; Tue, 28 Mar 2017 08:33:42 -0700 (PDT) From: To: Date: Tue, 28 Mar 2017 18:36:34 +0300 Message-ID: <1490715395-24751-3-git-send-email-kostap@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490715395-24751-1-git-send-email-kostap@marvell.com> References: <1490715395-24751-1-git-send-email-kostap@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-28_13:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703280131 Cc: Nadav Haklai , Stefan Roese , Igal Liberman Subject: [U-Boot] [PATCH 2/3] fix: mvebu: pcie_dw: Allow probing empty PCIe slots X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Konstantin Porotchkin This patch allows probing all PCIe nodes defined in DTS even if there no device connected to such node (no link). Without this fix the driver returns -ENODEV when the PCIe link is down. As result the pci_init function stops scanning bus on first empty PCIe slot and all devices located in higher numbered buses are not discovered. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Reviewed-by: Stefan Roese --- drivers/pci/pcie_dw_mvebu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index d4776a9..05a0660 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -487,13 +487,13 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) /* Don't register host if link is down */ if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) { printf("PCIE-%d: Link down\n", dev->seq); - return -ENODEV; + } else { + printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, + pcie_dw_get_link_speed(pcie->ctrl_base), + pcie_dw_get_link_width(pcie->ctrl_base), + hose->first_busno); } - printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, - pcie_dw_get_link_speed(pcie->ctrl_base), - pcie_dw_get_link_width(pcie->ctrl_base), hose->first_busno); - pcie_dw_regions_setup(pcie); /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */