From patchwork Fri Mar 24 18:24:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 743334 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vqX0W73yTz9s3w for ; Sat, 25 Mar 2017 05:25:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B2B47C21C75; Fri, 24 Mar 2017 18:25:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B5B0AC21C3F; Fri, 24 Mar 2017 18:24:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9ABA8C21C26; Fri, 24 Mar 2017 18:24:39 +0000 (UTC) Received: from mail.theobroma-systems.com (vegas.theobroma-systems.com [144.76.126.164]) by lists.denx.de (Postfix) with ESMTPS id 8439CC21C26 for ; Fri, 24 Mar 2017 18:24:38 +0000 (UTC) Received: from [86.59.122.178] (port=58172 helo=android.lan) by mail.theobroma-systems.com with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1crTt6-000614-H8; Fri, 24 Mar 2017 19:24:36 +0100 From: Philipp Tomsich To: u-boot@lists.denx.de Date: Fri, 24 Mar 2017 19:24:23 +0100 Message-Id: <1490379869-47505-2-git-send-email-philipp.tomsich@theobroma-systems.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490379869-47505-1-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1490379869-47505-1-git-send-email-philipp.tomsich@theobroma-systems.com> Cc: Philipp Tomsich , Klaus Goger Subject: [U-Boot] [PATCH 1/6] rockchip: pinctrl: rk3399: add GMAC (RGMII only) support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII * configures the RGMII pins (in GPIOC) when requested via pinctrl X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich Acked-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 37 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/pinctrl/rockchip/pinctrl_rk3399.c | 42 +++++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 4701cfb..8e20533 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -342,23 +342,60 @@ enum { GRF_UART0BT_SOUT = 1, /* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A0_SEL_SHIFT = 0, + GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, + GRF_MAC_TXD2 = 1, + GRF_GPIO3A1_SEL_SHIFT = 2, + GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, + GRF_MAC_TXD3 = 1, + GRF_GPIO3A2_SEL_SHIFT = 4, + GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, + GRF_MAC_RXD2 = 1, + GRF_GPIO3A3_SEL_SHIFT = 6, + GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, + GRF_MAC_RXD3 = 1, GRF_GPIO3A4_SEL_SHIFT = 8, GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_MAC_TXD0 = 1, GRF_SPI0NORCODEC_RXD = 2, GRF_GPIO3A5_SEL_SHIFT = 10, GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_MAC_TXD1 = 1, GRF_SPI0NORCODEC_TXD = 2, GRF_GPIO3A6_SEL_SHIFT = 12, GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_MAC_RXD0 = 1, GRF_SPI0NORCODEC_CLK = 2, GRF_GPIO3A7_SEL_SHIFT = 14, GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_MAC_RXD1 = 1, GRF_SPI0NORCODEC_CSN0 = 2, /* GRF_GPIO3B_IOMUX */ GRF_GPIO3B0_SEL_SHIFT = 0, GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_MAC_MDC = 1, GRF_SPI0NORCODEC_CSN1 = 2, + GRF_GPIO3B1_SEL_SHIFT = 2, + GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, + GRF_MAC_RXDV = 1, + GRF_GPIO3B3_SEL_SHIFT = 6, + GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, + GRF_MAC_CLK = 1, + GRF_GPIO3B4_SEL_SHIFT = 8, + GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, + GRF_MAC_TXEN = 1, + GRF_GPIO3B5_SEL_SHIFT = 10, + GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, + GRF_MAC_MDIO = 1, + GRF_GPIO3B6_SEL_SHIFT = 12, + GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, + GRF_MAC_RXCLK = 1, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C1_SEL_SHIFT = 2, + GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, + GRF_MAC_TXCLK = 1, /* GRF_GPIO4B_IOMUX */ GRF_GPIO4B0_SEL_SHIFT = 0, diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index fa6069b..239a274 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -38,6 +38,7 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_HDMI, + PERIPH_ID_GMAC, PERIPH_ID_COUNT, diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index a74793a..507bec4 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -202,6 +202,39 @@ static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) } } +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) +{ + rk_clrsetreg(&grf->gpio3a_iomux, + GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK | + GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK | + GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK | + GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK, + GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT | + GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT | + GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT | + GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT | + GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT | + GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT | + GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT | + GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3b_iomux, + GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK | + GRF_GPIO3B3_SEL_MASK | + GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK | + GRF_GPIO3B6_SEL_MASK, + GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT | + GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT | + GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT | + GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT | + GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT | + GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3c_iomux, + GRF_GPIO3C1_SEL_MASK, + GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); +} +#endif + static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); @@ -243,6 +276,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3399_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3399_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -283,6 +321,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_I2C5; case 65: return PERIPH_ID_SDMMC1; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 12: + return PERIPH_ID_GMAC; +#endif } #endif return -ENOENT;