From patchwork Mon Mar 20 20:48:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas MANOCHA X-Patchwork-Id: 741206 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vn83F32tjz9s06 for ; Tue, 21 Mar 2017 08:19:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 07BA4C21CC6; Mon, 20 Mar 2017 21:12:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 65C0BC21CE8; Mon, 20 Mar 2017 21:10:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BA679C21CB6; Mon, 20 Mar 2017 21:09:50 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 4439AC21CE6 for ; Mon, 20 Mar 2017 21:09:47 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id v2KL1Hw4005056; Mon, 20 Mar 2017 22:09:44 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 29ajhphmn1-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 20 Mar 2017 22:09:44 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 28CD731; Mon, 20 Mar 2017 21:09:44 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag7node3.st.com [10.75.127.21]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 145A34E4D; Mon, 20 Mar 2017 21:09:44 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG7NODE3.st.com (10.75.127.21) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Mon, 20 Mar 2017 22:09:43 +0100 From: Vikas Manocha To: Date: Mon, 20 Mar 2017 13:48:35 -0700 Message-ID: <1490042927-27450-10-git-send-email-vikas.manocha@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490042927-27450-1-git-send-email-vikas.manocha@st.com> References: <1490042927-27450-1-git-send-email-vikas.manocha@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG5NODE1.st.com (10.75.127.13) To SFHDAG7NODE3.st.com (10.75.127.21) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-20_15:, , signatures=0 Cc: Christophe KERELLO , Hans de Goede , Ian Campbell Subject: [U-Boot] [PATCH 09/18] ARM: DT: stm32f7: add gpio device tree nodes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Also created alias for gpios for stm32f7 discovery board. Based on these aliases, it would be possible to get gpio devices by sequence. Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- arch/arm/dts/stm32f746-disco.dts | 12 +++++ arch/arm/dts/stm32f746.dtsi | 111 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index f098d2e..f830aa9 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -65,6 +65,18 @@ aliases { serial0 = &usart1; spi0 = &qspi; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; }; }; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index e9fd6f4..865d5cf 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -114,6 +114,117 @@ u-boot,dm-pre-reloc; pins-are-numbered; + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x0 0x400>; + clocks = <&rcc 0 0>; + st,bank-name = "GPIOA"; + u-boot,dm-pre-reloc; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x400 0x400>; + clocks = <&rcc 0 1>; + st,bank-name = "GPIOB"; + u-boot,dm-pre-reloc; + }; + + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x800 0x400>; + clocks = <&rcc 0 2>; + st,bank-name = "GPIOC"; + u-boot,dm-pre-reloc; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0xc00 0x400>; + clocks = <&rcc 0 3>; + st,bank-name = "GPIOD"; + u-boot,dm-pre-reloc; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1000 0x400>; + clocks = <&rcc 0 4>; + st,bank-name = "GPIOE"; + u-boot,dm-pre-reloc; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1400 0x400>; + clocks = <&rcc 0 5>; + st,bank-name = "GPIOF"; + u-boot,dm-pre-reloc; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1800 0x400>; + clocks = <&rcc 0 6>; + st,bank-name = "GPIOG"; + u-boot,dm-pre-reloc; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 7>; + st,bank-name = "GPIOH"; + u-boot,dm-pre-reloc; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2000 0x400>; + clocks = <&rcc 0 8>; + st,bank-name = "GPIOI"; + u-boot,dm-pre-reloc; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2400 0x400>; + clocks = <&rcc 0 9>; + st,bank-name = "GPIOJ"; + u-boot,dm-pre-reloc; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2800 0x400>; + clocks = <&rcc 0 10>; + st,bank-name = "GPIOK"; + u-boot,dm-pre-reloc; + }; + usart1_pins_a: usart1@0 { pins1 { pinmux = ;