From patchwork Wed Feb 22 09:47:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 731177 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vT1pT5Dtnz9s7F for ; Thu, 23 Feb 2017 02:42:41 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 60470B38FD; Wed, 22 Feb 2017 16:42:40 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aUqsPrn0td8J; Wed, 22 Feb 2017 16:42:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2145EB38CD; Wed, 22 Feb 2017 16:32:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 246114B5B9 for ; Wed, 22 Feb 2017 10:58:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yL8V0EJM3O-D for ; Wed, 22 Feb 2017 10:58:42 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by theia.denx.de (Postfix) with ESMTPS id 3A0BB4B5B1 for ; Wed, 22 Feb 2017 10:58:36 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Feb 2017 01:48:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,193,1484035200"; d="scan'208";a="936769314" Received: from unknown (HELO ubuntu.png.intel.com) ([10.226.248.66]) by orsmga003.jf.intel.com with ESMTP; 22 Feb 2017 01:48:18 -0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Wed, 22 Feb 2017 17:47:23 +0800 Message-Id: <1487756858-16730-6-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487756858-16730-1-git-send-email-ley.foon.tan@intel.com> References: <1487756858-16730-1-git-send-email-ley.foon.tan@intel.com> X-Mailman-Approved-At: Wed, 22 Feb 2017 16:24:23 +0100 Cc: Tien Fong Chee , Chin Liang See Subject: [U-Boot] [PATCH 05/20] arm: socfpga: add A10 defines X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" add i2c, timer and other A10 defines. Signed-off-by: Dinh Nguyen Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4..d3dea0b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Altera Corporation + * Copyright (C) 2014-2017 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -29,14 +29,20 @@ #define SOCFPGA_MPUL2_ADDRESS 0xfffff000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SDR_ADDRESS 0xffcfb000 +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000 +#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300