From patchwork Sat Feb 4 22:43:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas MANOCHA X-Patchwork-Id: 724158 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vG8TP6yC2z9ryk for ; Sun, 5 Feb 2017 10:05:13 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58FC5A7779; Sun, 5 Feb 2017 00:04:50 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VRJhd9Eox_bH; Sun, 5 Feb 2017 00:04:50 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C94B4B387E; Sun, 5 Feb 2017 00:04:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 54AA8A775C for ; Sun, 5 Feb 2017 00:04:20 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zSRJppp6cBqY for ; Sun, 5 Feb 2017 00:04:20 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by theia.denx.de (Postfix) with ESMTPS id DAA50A7746 for ; Sun, 5 Feb 2017 00:04:14 +0100 (CET) Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id v14N3cPn008562; Sun, 5 Feb 2017 00:04:10 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 28d5a1ubb6-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 05 Feb 2017 00:04:10 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6F28A34; Sat, 4 Feb 2017 23:04:04 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag7node3.st.com [10.75.127.21]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 56286168D; Sat, 4 Feb 2017 23:04:04 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG7NODE3.st.com (10.75.127.21) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Sun, 5 Feb 2017 00:04:03 +0100 From: Vikas Manocha To: Date: Sat, 4 Feb 2017 14:43:39 -0800 Message-ID: <1486248221-20978-9-git-send-email-vikas.manocha@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1486248221-20978-1-git-send-email-vikas.manocha@st.com> References: <1486248221-20978-1-git-send-email-vikas.manocha@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG4NODE1.st.com (10.75.127.10) To SFHDAG7NODE3.st.com (10.75.127.21) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-04_20:, , signatures=0 Cc: Albert Aribaud , Ian Campbell , Hans de Goede Subject: [U-Boot] [PATCH 08/10] ARM: DT: stm32f7: add pin control node for serial port pins X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" And remove the uart pin configuration from board initialization. Signed-off-by: Vikas Manocha --- arch/arm/dts/stm32f746-disco.dts | 6 ++++++ arch/arm/dts/stm32f746.dtsi | 13 +++++++++++++ board/st/stm32f746-disco/stm32f746-disco.c | 25 +------------------------ 3 files changed, 20 insertions(+), 24 deletions(-) diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 454b515..6734f23 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -70,6 +70,12 @@ clock-frequency = <25000000>; }; +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + &mac { status = "okay"; phy-mode = "rmii"; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index f59eca8..867f399 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -104,6 +104,19 @@ ranges = <0 0x40020000 0x3000>; u-boot,dm-pre-reloc; pins-are-numbered; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; }; }; }; diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index ee1deb5..9ebc36b 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -27,14 +27,6 @@ const struct stm32_gpio_ctl gpio_ctl_gpout = { .af = STM32_GPIO_AF0 }; -const struct stm32_gpio_ctl gpio_ctl_usart = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_50M, - .pupd = STM32_GPIO_PUPD_UP, - .af = STM32_GPIO_AF7 -}; - const struct stm32_gpio_ctl gpio_ctl_fmc = { .mode = STM32_GPIO_MODE_AF, .otype = STM32_GPIO_OTYPE_PP, @@ -245,26 +237,11 @@ int dram_init(void) return rv; } -static const struct stm32_gpio_dsc usart_gpio[] = { - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ - {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ -}; - int uart_setup_gpio(void) { - int i; - int rv = 0; - clock_setup(GPIO_A_CLOCK_CFG); clock_setup(GPIO_B_CLOCK_CFG); - for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { - rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); - if (rv) - goto out; - } - -out: - return rv; + return 0; } #ifdef CONFIG_ETH_DESIGNWARE