From patchwork Tue Jan 17 15:27:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Herbrechtsmeier Dr.-Ing. , Stefan" X-Patchwork-Id: 716235 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3v2vBv57y3z9ryn for ; Wed, 18 Jan 2017 02:28:39 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 44F94A7600; Tue, 17 Jan 2017 16:28:38 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jqjCujCxVpn3; Tue, 17 Jan 2017 16:28:38 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A0126B3881; Tue, 17 Jan 2017 16:28:37 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D3E31B38B7 for ; Tue, 17 Jan 2017 16:28:35 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9xgy9AikpaGZ for ; Tue, 17 Jan 2017 16:28:35 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail2.weidmueller.de (mail2.weidmueller.de [217.244.7.241]) by theia.denx.de (Postfix) with ESMTP id DD192B38BA for ; Tue, 17 Jan 2017 16:28:31 +0100 (CET) Received: from SRVDE354.weidmueller.com (unknown [10.1.23.126]) by mail2.weidmueller.de with smtp id 52ec_5771_eaacf41f_c183_406a_b287_9bb36e4b2b74; Tue, 17 Jan 2017 16:28:24 +0100 Received: from w010094-VirtualBox.weidmueller.com (10.1.94.106) by SRVDE354.weidmueller.com (10.1.23.126) with Microsoft SMTP Server id 14.3.294.0; Tue, 17 Jan 2017 16:28:10 +0100 From: To: Date: Tue, 17 Jan 2017 16:27:25 +0100 Message-ID: <1484666853-19282-3-git-send-email-stefan.herbrechtsmeier@weidmueller.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484666853-19282-1-git-send-email-stefan.herbrechtsmeier@weidmueller.com> References: <1484666853-19282-1-git-send-email-stefan.herbrechtsmeier@weidmueller.com> MIME-Version: 1.0 X-NAIMIME-Disclaimer: 1 X-NAIMIME-Modified: 1 X-NAI-Spam-Flag: NO X-NAI-Spam-Threshold: 4 X-NAI-Spam-Score: 0 X-NAI-Spam-Version: 2.3.0.9418 : core <5922> : inlines <5632> : streams <1729480> : uri <2359648> Cc: Joe Hershberger , Albert Aribaud , Michal Simek Subject: [U-Boot] [PATCH v2 02/10] net: zynq: Add clk framework support to zynq ethernet driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Herbrechtsmeier If available use the clock framework to set the tx clock rate of the zynq ethernet controller. Signed-off-by: Stefan Herbrechtsmeier Reviewed-by: Joe Hershberger --- Changes in v2: - Rebase arch/arm/include/asm/arch-zynqmp/sys_proto.h | 7 ------- drivers/net/zynq_gem.c | 22 +++++++++++++++------- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 8c54fce..7b11895 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,13 +8,6 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H -#ifndef CONFIG_CLK_ZYNQMP -/* Setup clk for network */ -static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) -{ -} -#endif - int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 872e4f8..8c5c55a 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -181,7 +181,7 @@ struct zynq_gem_priv { struct phy_device *phydev; int phy_of_handle; struct mii_dev *bus; -#ifdef CONFIG_CLK_ZYNQMP +#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) struct clk clk; #endif }; @@ -456,13 +456,21 @@ static int zynq_gem_init(struct udevice *dev) break; } -#ifndef CONFIG_CLK_ZYNQMP +#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) + ret = clk_set_rate(&priv->clk, clk_rate); + if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { + dev_err(dev, "failed to set tx clock rate\n"); + return ret; + } + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable tx clock\n"); + return ret; + } +#else zynq_slcr_gem_clk_setup((ulong)priv->iobase != ZYNQ_GEM_BASEADDR0, clk_rate); -#else - ret = clk_set_rate(&priv->clk, clk_rate); - if (IS_ERR_VALUE(ret)) - return -1; #endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | @@ -636,7 +644,7 @@ static int zynq_gem_probe(struct udevice *dev) priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); -#ifdef CONFIG_CLK_ZYNQMP +#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) ret = clk_get_by_name(dev, "tx_clk", &priv->clk); if (ret < 0) { dev_err(dev, "failed to get clock\n");