| Message ID | 1484666853-19282-10-git-send-email-stefan.herbrechtsmeier@weidmueller.com |
|---|---|
| State | Accepted |
| Commit | e0f4de1afcdb80b4ccad10a877504baaeb7ae2c0 |
| Delegated to: | Michal Simek |
| Headers | show |
On 01/18/2017 12:27 AM, stefan.herbrechtsmeier@weidmueller.com wrote: > From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> > > The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base > clock frequency but this clock is not fixed and depends on the hardware > configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ > doesn't match the real base clock frequency of SDIO_FREQ. Use the clock > framework to determine the frequency at run time. > > Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung > > --- > > Changes in v2: > - Add patch to determine base clock frequency of zynq mmc driver via > clock framework > > drivers/mmc/zynq_sdhci.c | 26 ++++++++++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c > index 69efa38..c73a4d3 100644 > --- a/drivers/mmc/zynq_sdhci.c > +++ b/drivers/mmc/zynq_sdhci.c > @@ -6,6 +6,7 @@ > * SPDX-License-Identifier: GPL-2.0+ > */ > > +#include <clk.h> > #include <common.h> > #include <dm.h> > #include <fdtdec.h> > @@ -27,8 +28,29 @@ static int arasan_sdhci_probe(struct udevice *dev) > struct arasan_sdhci_plat *plat = dev_get_platdata(dev); > struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); > struct sdhci_host *host = dev_get_priv(dev); > + struct clk clk; > + unsigned long clock; > int ret; > > + ret = clk_get_by_index(dev, 0, &clk); > + if (ret < 0) { > + dev_err(dev, "failed to get clock\n"); > + return ret; > + } > + > + clock = clk_get_rate(&clk); > + if (IS_ERR_VALUE(clock)) { > + dev_err(dev, "failed to get rate\n"); > + return clock; > + } > + debug("%s: CLK %ld\n", __func__, clock); > + > + ret = clk_enable(&clk); > + if (ret && ret != -ENOSYS) { > + dev_err(dev, "failed to enable clock\n"); > + return ret; > + } > + > host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | > SDHCI_QUIRK_BROKEN_R1B; > > @@ -36,9 +58,9 @@ static int arasan_sdhci_probe(struct udevice *dev) > host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; > #endif > > - host->max_clk = CONFIG_ZYNQ_SDHCI_MAX_FREQ; > + host->max_clk = clock; > > - ret = sdhci_setup_cfg(&plat->cfg, host, 0, > + ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, > CONFIG_ZYNQ_SDHCI_MIN_FREQ); > host->mmc = &plat->mmc; > if (ret) >
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 69efa38..c73a4d3 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <clk.h> #include <common.h> #include <dm.h> #include <fdtdec.h> @@ -27,8 +28,29 @@ static int arasan_sdhci_probe(struct udevice *dev) struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); + struct clk clk; + unsigned long clock; int ret; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; @@ -36,9 +58,9 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; #endif - host->max_clk = CONFIG_ZYNQ_SDHCI_MAX_FREQ; + host->max_clk = clock; - ret = sdhci_setup_cfg(&plat->cfg, host, 0, + ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, CONFIG_ZYNQ_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; if (ret)