From patchwork Wed Dec 28 06:34:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 709171 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tpNVJ0WTRz9sCX for ; Wed, 28 Dec 2016 17:43:36 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6B7A4B3970; Wed, 28 Dec 2016 07:41:56 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UJB-oV9eer2Q; Wed, 28 Dec 2016 07:41:56 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 64DB2B39BA; Wed, 28 Dec 2016 07:41:49 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 48832B397B for ; Wed, 28 Dec 2016 07:41:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8Tq-lf25sZyS for ; Wed, 28 Dec 2016 07:41:28 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by theia.denx.de (Postfix) with ESMTPS id 5DCD6B3998 for ; Wed, 28 Dec 2016 07:41:15 +0100 (CET) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP; 27 Dec 2016 22:41:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,421,1477983600"; d="scan'208";a="47354193" Received: from unknown (HELO chee-tien-fong.png.intel.com) ([10.226.249.227]) by fmsmga005.fm.intel.com with ESMTP; 27 Dec 2016 22:41:11 -0800 From: Chee Tien Fong To: u-boot@lists.denx.de Date: Wed, 28 Dec 2016 14:34:39 +0800 Message-Id: <1482906881-8120-28-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482906881-8120-1-git-send-email-tien.fong.chee@intel.com> References: <1482906881-8120-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Chin Liang See , Tien Fong Subject: [U-Boot] [PATCH v2 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Removed extern declaration. --- arch/arm/mach-socfpga/include/mach/pinmux.h | 17 +++++ arch/arm/mach-socfpga/pinmux.c | 104 ++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h create mode 100644 arch/arm/mach-socfpga/pinmux.c diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h new file mode 100644 index 0000000..ff54caa --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _PINMUX_H_ +#define _PINMUX_H_ + +#ifndef __ASSEMBLY__ +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +#endif + + + +#endif /* _PINMUX_H_ */ diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c new file mode 100644 index 0000000..d45722f --- /dev/null +++ b/arch/arm/mach-socfpga/pinmux.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +static int __do_pinctr_pins(const void *blob, int child, const char *node_name); +static int do_pinctrl_pins(const void *blob, int node, const char *child_name); + +static int __do_pinctr_pins(const void *blob, int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr; + fdt_size_t size; + const u32 *cell; + u32 offset, value; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", + &len); + if (cell != NULL) { + debug("%p %d\n", cell, len); + for (;len > 0; len -= (2*sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + debug("<0x%x 0x%x>\n", offset, value); + writel(value, base_addr + offset); + } + return 0; + } + } + return 1; +} + +static int do_pinctrl_pins(const void *blob, int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return 2; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(child_name, node_name)) { + __do_pinctr_pins(blob, child, node_name); + return(0); + } + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return 1; +} + +int config_dedicated_pins(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 1; + + if (do_pinctrl_pins(blob, node, "dedicated_cfg")) + return 2; + + if (do_pinctrl_pins(blob, node, "dedicated")) + return 3; + + return 0; +} + +int config_pins(const void *blob, const char *pin_grp) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 1; + + if (do_pinctrl_pins(blob, node, pin_grp)) + return 2; + + return 0; +}