From patchwork Mon Dec 19 15:04:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kostya Porotchkin X-Patchwork-Id: 707115 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tj4053rQ4z9vFT for ; Tue, 20 Dec 2016 02:02:28 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4A4FEB38B9; Mon, 19 Dec 2016 16:02:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K_mgn22tmCqy; Mon, 19 Dec 2016 16:02:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B68B7B387C; Mon, 19 Dec 2016 16:02:23 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AF5B4B387C for ; Mon, 19 Dec 2016 16:02:19 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JClNDz0bXaVE for ; Mon, 19 Dec 2016 16:02:19 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by theia.denx.de (Postfix) with ESMTPS id 29BA3B3864 for ; Mon, 19 Dec 2016 16:02:15 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id uBJF0C6E021198; Mon, 19 Dec 2016 07:02:12 -0800 Received: from il-exch01.marvell.com ([199.203.130.101]) by mx0b-0016f401.pphosted.com with ESMTP id 27ebh4a9vg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 19 Dec 2016 07:02:11 -0800 Received: from SC-EXCH02.marvell.com (10.93.176.82) by IL-EXCH01.marvell.com (10.4.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 19 Dec 2016 17:02:08 +0200 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 19 Dec 2016 07:02:07 -0800 Received: from Malogato.pt.marvell.com (unknown [10.5.24.37]) by maili.marvell.com (Postfix) with ESMTP id DB3873F7043; Mon, 19 Dec 2016 07:02:05 -0800 (PST) From: To: Date: Mon, 19 Dec 2016 17:04:42 +0200 Message-ID: <1482159882-3955-1-git-send-email-kostap@marvell.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-19_11:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1612190196 Cc: Haim Boot , Hanna Hawa , Omri Itach , Nadav Haklai , Neta Zur Hershkovits , Stefan Roese , Igal Liberman Subject: [U-Boot] [PATCH v2] arm64: mvebu: Fix A8K memory mapping and add documentation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Konstantin Porotchkin Fix the MMU mapping for A8K device family: - Separate A7K and A8K memory mappings - Fix memory regions by including IO mapping for all 3 PCIe interfaces existing on each connected CP110 controller Add A8K memory mapping documentation with all regions configured by Marvell ATF. Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6 Signed-off-by: Konstantin Porotchkin Signed-off-by: Stefan Roese Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa --- Changes for v2: - Exclude CP1 memory regions from A7K MMU map - Dynamically adjust the MMU regions list according to the platform type arch/arm/mach-mvebu/armada8k/cpu.c | 58 +++++++++++++++++++++++++++++--------- doc/mvebu/armada-8k-memory.txt | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+), 13 deletions(-) create mode 100644 doc/mvebu/armada-8k-memory.txt diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 2719d68..2325e9a 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -21,7 +21,33 @@ DECLARE_GLOBAL_DATA_PTR; #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84) #define RFU_SW_RESET_OFFSET 0 +/* + * The following table includes all memory regions for Armada 7k and + * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets + * define these regions at the beginning of the struct so that they + * can be easier removed later dynamically if an Armada 7k device is detected. + * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt + */ +#define ARMADA_7K8K_COMMON_REGIONS_START 2 static struct mm_region mvebu_mem_map[] = { + /* Armada 80x0 memory regions include the CP1 (slave) units */ + { + /* SRAM, MMIO regions - CP110 slave region */ + .phys = 0xf4000000UL, + .virt = 0xf4000000UL, + .size = 0x02000000UL, /* 32MiB internal registers */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { + /* PCI CP1 regions */ + .phys = 0xfa000000UL, + .virt = 0xfa000000UL, + .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + /* Armada 80x0 and 70x0 common memory regions start here */ { /* RAM */ .phys = 0x0UL, @@ -47,29 +73,35 @@ static struct mm_region mvebu_mem_map[] = { PTE_BLOCK_NON_SHARE }, { - /* SRAM, MMIO regions - CP110 slave region */ - .phys = 0xf4000000UL, - .virt = 0xf4000000UL, - .size = 0x02000000UL, /* 32MiB internal registers */ + /* PCI CP0 regions */ + .phys = 0xf6000000UL, + .virt = 0xf6000000UL, + .size = 0x04000000UL, /* 64MiB CP110 master PCI space */ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, { - /* PCI regions */ - .phys = 0xf8000000UL, - .virt = 0xf8000000UL, - .size = 0x08000000UL, /* 128MiB PCI space (master & slave) */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* List terminator */ 0, } }; struct mm_region *mem_map = mvebu_mem_map; +void enable_caches(void) +{ + /* + * Armada 7k is not equipped with the CP110 slave CP. In case this + * code runs on an Armada 7k device, lets remove the CP110 slave + * entries from the memory mapping by moving the start to the + * common regions. + */ + if (of_machine_is_compatible("marvell,armada7040")) + mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START]; + + icache_enable(); + dcache_enable(); +} + void reset_cpu(ulong ignored) { u32 reg; diff --git a/doc/mvebu/armada-8k-memory.txt b/doc/mvebu/armada-8k-memory.txt new file mode 100644 index 0000000..064518e --- /dev/null +++ b/doc/mvebu/armada-8k-memory.txt @@ -0,0 +1,56 @@ + Memory Layout on Armada-8k SoC's + ================================ + +The below desribes the physical memory layout for Marvell's Armada-8k SoC's. + +This assumes that the SoC includes Dual CP configuration, in case the flavor is using +a single CP configuration, then all secondary-CP mappings are invalid. + +All "Reserved" areas below, are kept for future usage. + +Start End Use +-------------------------------------------------------------------------- +0x00000000 0xEFFFFFFF DRAM + +0xF0000000 0xF0FFFFFF AP Internal registers space + +0xF1000000 0xF1FFFFFF Reserved. + +0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers + space. + +0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers + space. + +0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space. + +0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space. + +0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space. + +0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space. + +0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space. + +0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space. + +0xF9030000 0xF9FFFFFF Reserved. + +0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space. + +0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space. + +0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space. + +0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space. + +0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space. + +0xFD020000 0xFD02FFFF CP-1 / PCIe#2 IO space. + +0xFD030000 0xFFEFFFFF Reserved. + +0xFFF00000 0xFFFFFFFF Bootrom + +0x100000000 -1 DRAM +