From patchwork Thu Dec 15 17:35:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 706195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tfgbq5kt8z9sCM for ; Fri, 16 Dec 2016 04:36:39 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3180FA75BF; Thu, 15 Dec 2016 18:36:37 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WF-vnHOGA8fO; Thu, 15 Dec 2016 18:36:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8B637A75AC; Thu, 15 Dec 2016 18:36:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7106AA75AC for ; Thu, 15 Dec 2016 18:36:33 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7gMiJ-uUp8jN for ; Thu, 15 Dec 2016 18:36:33 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by theia.denx.de (Postfix) with ESMTPS id 36702A7576 for ; Thu, 15 Dec 2016 18:36:28 +0100 (CET) Received: by mail-wm0-f66.google.com with SMTP id a20so7951939wme.2 for ; Thu, 15 Dec 2016 09:36:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+imVnWPePzSqssOWb5/OugUvEp/VZZEgErlj7FiGvh4=; b=sA90tmmAvFT9/pX5yrgIwnzQy1lnF9kcJVZN8j8kCNcoB9VljMtVPdYLR0BJrjSCz8 miQPdfa0BidNY7jQ/iGCJA6KjcP6S1MBJZu+wRBcVHbj01wt4HJfoGvILrZR//qBG9Gu RVjNh9wMN9n8Zw3/uERswUpEMfQFyjgC69pmzsn5ioY/e6e3EdLjp9cTdbhzwb/TLVDT F+i44+uR9PSugVTwNNGUFHo7wNvVeEGcV2ucUbLexyO9wEnzSSn24GQICE+ZYAJ9Xiwv W93oe3c+EaajcKsDXEQn2yuuhZLJBLaURsOvRS3iFl4ngz0ir4laYM773rPcAA0dKh5+ IVXA== X-Gm-Message-State: AIkVDXIKzjiW+GpDeE9Dip2wsbo8xQrrC9aXqjQ8egY8uFagyc1Mq/IoUHrNpjyAoTO0TA== X-Received: by 10.28.113.218 with SMTP id d87mr2496102wmi.111.1481823388399; Thu, 15 Dec 2016 09:36:28 -0800 (PST) Received: from localhost.localdomain ([185.97.14.22]) by smtp.gmail.com with ESMTPSA id d184sm3407063wmd.8.2016.12.15.09.36.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Dec 2016 09:36:27 -0800 (PST) From: Jagan Teki To: u-boot@lists.denx.de Date: Thu, 15 Dec 2016 18:35:56 +0100 Message-Id: <1481823356-17086-1-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 Cc: Jagan Teki Subject: [U-Boot] [PATCH v2] Revert "sf: Fix quad bit set for micron devices" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Cyrille Pitchen This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe. Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted. Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence. Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails. Indeed the SPI controller driver is not aware of the SPI protocol switch. Further patches will fix the support of Micron QSPI memories. Signed-off-by: Cyrille Pitchen [Rebase on master, use JEDEC_MFR(info) in place of idcode0] Signed-off-by: Jagan Teki --- Changes for v2: - Rebase and JEDEC_MFR(info) in place of idcode0 drivers/mtd/spi/sf_internal.h | 3 --- drivers/mtd/spi/spi_flash.c | 62 ++----------------------------------------- 2 files changed, 2 insertions(+), 63 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 2463686..839cdbe 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -49,7 +49,6 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 -#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -63,7 +62,6 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 -#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -78,7 +76,6 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) -#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index b902540..2e378dc 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -112,37 +112,6 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif -#ifdef CONFIG_SPI_FLASH_STMICRO -static int read_evcr(struct spi_flash *flash, u8 *evcr) -{ - int ret; - const u8 cmd = CMD_READ_EVCR; - - ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); - if (ret < 0) { - debug("SF: error reading EVCR\n"); - return ret; - } - - return 0; -} - -static int write_evcr(struct spi_flash *flash, u8 evcr) -{ - u8 cmd; - int ret; - - cmd = CMD_WRITE_EVCR; - ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); - if (ret < 0) { - debug("SF: error while writing EVCR register\n"); - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_SPI_FLASH_BAR static int write_bar(struct spi_flash *flash, u32 offset) { @@ -894,34 +863,6 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif -#ifdef CONFIG_SPI_FLASH_STMICRO -static int micron_quad_enable(struct spi_flash *flash) -{ - u8 qeb_status; - int ret; - - ret = read_evcr(flash, &qeb_status); - if (ret < 0) - return ret; - - if (!(qeb_status & STATUS_QEB_MICRON)) - return 0; - - ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); - if (ret < 0) - return ret; - - /* read EVCR and check it */ - ret = read_evcr(flash, &qeb_status); - if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { - printf("SF: Micron EVCR Quad bit not clear\n"); - return -EINVAL; - } - - return ret; -} -#endif - static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) { int tmp; @@ -962,7 +903,8 @@ static int set_quad_mode(struct spi_flash *flash, #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - return micron_quad_enable(flash); + debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); + return 0; #endif default: printf("SF: Need set QEB func for %02x flash\n",