From patchwork Tue Dec 6 08:11:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 703113 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tY0zD1Yt4z9vKg for ; Tue, 6 Dec 2016 23:18:48 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4855BA7665; Tue, 6 Dec 2016 13:17:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id w98AEbjis8GO; Tue, 6 Dec 2016 13:17:34 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1C898A766A; Tue, 6 Dec 2016 13:16:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6C261A7599 for ; Tue, 6 Dec 2016 09:11:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wDp_vI51MDGF for ; Tue, 6 Dec 2016 09:11:36 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by theia.denx.de (Postfix) with ESMTPS id 9D634A7573 for ; Tue, 6 Dec 2016 09:11:35 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP; 06 Dec 2016 00:11:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,309,1477983600"; d="scan'208";a="794732792" Received: from unknown (HELO chee-tien-fong.png.intel.com) ([10.226.250.18]) by FMSMGA003.fm.intel.com with ESMTP; 06 Dec 2016 00:11:31 -0800 From: Chee Tien Fong To: u-boot@lists.denx.de Date: Tue, 6 Dec 2016 16:11:24 +0800 Message-Id: <1481011884-3841-1-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 X-Mailman-Approved-At: Tue, 06 Dec 2016 13:16:25 +0100 Cc: Marek Vasut , Tien Fong Chee , Chin Liang See , Tien Fong Subject: [U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/spl.c | 86 +++++++++++++++++++++++++++++++++++++++++- 1 files changed, 83 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a..9375514 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -1,7 +1,7 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */ #include @@ -19,22 +19,32 @@ #include #include #include +#include +#include +#include +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) switch (bsel & 0x7) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; @@ -55,6 +65,24 @@ u32 spl_boot_device(void) printf("Invalid boot device (bsel=%08x)!\n", bsel); hang(); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + switch ((bsel>>12) & 0x7) { + case 0x1: /* FPGA (HPS2FPGA Bridge) */ + return BOOT_DEVICE_RAM; + case 0x2: /* NAND Flash (1.8V) */ + case 0x3: /* NAND Flash (3.0V) */ + return BOOT_DEVICE_NAND; + case 0x4: /* SD/MMC External Transceiver (1.8V) */ + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ + return BOOT_DEVICE_MMC1; + case 0x6: /* QSPI Flash (1.8V) */ + case 0x7: /* QSPI Flash (3.0V) */ + return BOOT_DEVICE_SPI; + default: + printf("Invalid boot device (bsel=%08x)!\n", bsel); + hang(); + } +#endif } #ifdef CONFIG_SPL_MMC_SUPPORT @@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -182,3 +211,54 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void board_init_f(ulong dummy) +{ + memset(__bss_start, 0, __bss_end - __bss_start); + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_OF_CONTROL + /* We need to access to FDT as this stage */ + /* FDT is at end of image */ + gd->fdt_blob = (void *)(__bss_end); + /* Check whether we have a valid FDT or not. */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } +#endif /* CONFIG_OF_CONTROL */ + + /* Initialize the timer */ + timer_init(); + + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* configure the Reset Manager */ + reset_deassert_dedicated_peripherals(); + + /* enable console uart printing */ + preloader_console_init(); +} +#endif