From patchwork Tue Dec 6 07:52:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 703108 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tY0xK5q50z9vKN for ; Tue, 6 Dec 2016 23:17:09 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 280ADA7607; Tue, 6 Dec 2016 13:16:57 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xIA6mu521I0s; Tue, 6 Dec 2016 13:16:57 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0F6DAA75E6; Tue, 6 Dec 2016 13:16:37 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C8475A7573 for ; Tue, 6 Dec 2016 09:04:18 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YZZOIbspdL7U for ; Tue, 6 Dec 2016 09:04:18 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by theia.denx.de (Postfix) with ESMTPS id 297C44BA81 for ; Tue, 6 Dec 2016 09:04:14 +0100 (CET) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP; 05 Dec 2016 23:53:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,309,1477983600"; d="scan'208";a="37448562" Received: from unknown (HELO chee-tien-fong.png.intel.com) ([10.226.250.18]) by orsmga004.jf.intel.com with ESMTP; 05 Dec 2016 23:53:19 -0800 From: Chee Tien Fong To: u-boot@lists.denx.de Date: Tue, 6 Dec 2016 15:52:41 +0800 Message-Id: <1481010767-3325-3-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1481010767-3325-1-git-send-email-tien.fong.chee@intel.com> References: <1481010767-3325-1-git-send-email-tien.fong.chee@intel.com> X-Mailman-Approved-At: Tue, 06 Dec 2016 13:16:25 +0100 Cc: Marek Vasut , Tien Fong Chee , Chin Liang See , Tien Fong Subject: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- include/fdtdec.h | 8 ++++++++ lib/fdtdec.c | 2 ++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 27887c8..68cb199 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,6 +155,14 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* Arria10 hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, /* Arria10 lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* Arria10 fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* Arria10 fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* Arria10 fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* Arria10 fpga2SDRAM2 bridge */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4defb90..09a1db4 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,6 +66,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id)