From patchwork Thu Dec 1 15:14:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yehuda Yitschak X-Patchwork-Id: 701559 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tV18X6Syxz9t1L for ; Fri, 2 Dec 2016 02:16:28 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6A9DCA75CD; Thu, 1 Dec 2016 16:16:20 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r5g-oEZt5qdx; Thu, 1 Dec 2016 16:16:20 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37523A75BF; Thu, 1 Dec 2016 16:16:18 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9600DA757A for ; Thu, 1 Dec 2016 16:16:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8FRBzJuH46Ef for ; Thu, 1 Dec 2016 16:16:12 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by theia.denx.de (Postfix) with ESMTPS id 31151A7576 for ; Thu, 1 Dec 2016 16:16:09 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uB1F4pc5001921; Thu, 1 Dec 2016 07:16:02 -0800 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-0016f401.pphosted.com with ESMTP id 26yasn0eby-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 01 Dec 2016 07:16:02 -0800 Received: from m0045851.ppops.net (m0045851.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.16/8.16.0.16) with SMTP id uB1FG19p007825; Thu, 1 Dec 2016 07:16:01 -0800 Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 26yasn0ebw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 01 Dec 2016 07:16:01 -0800 Received: from IL-EXCH03.marvell.com (10.5.102.220) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Thu, 1 Dec 2016 07:15:59 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by IL-EXCH03.marvell.com (10.5.102.220) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Thu, 1 Dec 2016 17:15:56 +0200 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1104.5 via Frontend Transport; Thu, 1 Dec 2016 07:15:56 -0800 Received: from Dude.il.marvell.com (unknown [10.4.50.6]) by maili.marvell.com (Postfix) with ESMTP id 175673F7040; Thu, 1 Dec 2016 07:15:53 -0800 (PST) From: To: , , , , , , , Date: Thu, 1 Dec 2016 17:14:18 +0200 Message-ID: <1480605258-30773-2-git-send-email-yehuday@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480605258-30773-1-git-send-email-yehuday@marvell.com> References: <1480605258-30773-1-git-send-email-yehuday@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-01_12:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609300000 definitions=main-1612010259 Subject: [U-Boot] [PATCH v4 1/1] cmd: pci: add option to parse and display BAR information X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Yehuda Yitschak Currently the PCI command only allows to see the BAR register values but not the size and actual base address. This little extension parses the BAR registers and displays the base, size and type of each BAR. Signed-off-by: Yehuda Yitschak Reviewed-by: Simon Glass --- cmd/pci.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/cmd/pci.c b/cmd/pci.c index 2f4978a..7993c1a 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -92,6 +92,77 @@ static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs) } #endif +#ifdef CONFIG_DM_PCI +int pci_bar_show(struct udevice *dev) +{ + u8 header_type; + int bar_cnt, bar_id, mem_type; + bool is_64, is_io; + u32 base_low, base_high; + u32 size_low, size_high; + u64 base, size; + u32 reg_addr; + int prefetchable; + + dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + + if (header_type == PCI_HEADER_TYPE_CARDBUS) { + printf("CardBus doesn't support BARs\n"); + return -ENOSYS; + } + + bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2; + + printf("ID Base Size Width Type\n"); + printf("----------------------------------------------------------\n"); + + bar_id = 0; + reg_addr = PCI_BASE_ADDRESS_0; + while (bar_cnt) { + dm_pci_read_config32(dev, reg_addr, &base_low); + dm_pci_write_config32(dev, reg_addr, 0xffffffff); + dm_pci_read_config32(dev, reg_addr, &size_low); + dm_pci_write_config32(dev, reg_addr, base_low); + reg_addr += 4; + + base = base_low & ~0xf; + size = size_low & ~0xf; + base_high = 0x0; + size_high = 0xffffffff; + is_64 = 0; + prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH; + is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO; + mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK; + + if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) { + dm_pci_read_config32(dev, reg_addr, &base_high); + dm_pci_write_config32(dev, reg_addr, 0xffffffff); + dm_pci_read_config32(dev, reg_addr, &size_high); + dm_pci_write_config32(dev, reg_addr, base_high); + bar_cnt--; + reg_addr += 4; + is_64 = 1; + } + + base = base | ((u64)base_high << 32); + size = size | ((u64)size_high << 32); + + if ((!is_64 && size_low) || (is_64 && size)) { + size = ~size + 1; + printf(" %d %#016llx %#016llx %d %s %s\n", + bar_id, base, size, is_64 ? 64 : 32, + is_io ? "I/O" : "MEM", + prefetchable ? "Prefetchable" : ""); + } + + bar_id++; + bar_cnt--; + } + + return 0; +} +#endif + static struct pci_reg_info regs_start[] = { { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID }, { "device ID", PCI_SIZE_16, PCI_DEVICE_ID }, @@ -573,6 +644,9 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 4) value = simple_strtoul(argv[4], NULL, 16); case 'h': /* header */ +#ifdef CONFIG_DM_PCI + case 'b': /* bars */ +#endif if (argc < 3) goto usage; if ((bdf = get_pci_dev(argv[2])) == -1) @@ -641,6 +715,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ret = pci_cfg_write(dev, addr, size, value); #endif break; +#ifdef CONFIG_DM_PCI + + case 'b': /* bars */ + return pci_bar_show(dev); +#endif default: ret = CMD_RET_USAGE; break; @@ -663,6 +742,10 @@ static char pci_help_text[] = #endif "pci header b.d.f\n" " - show header of PCI device 'bus.device.function'\n" +#ifdef CONFIG_DM_PCI + "pci bar b.d.f\n" + " - show BARs base and size for device b.d.f'\n" +#endif "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" " - display PCI configuration space (CFG)\n" "pci next[.b, .w, .l] b.d.f address\n"