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[U-Boot,1/9] ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoC

Message ID 1475900731-10998-2-git-send-email-yamada.masahiro@socionext.com
State Accepted
Commit 6c22742d3defa76be00b4d3b5b49911fa63ffa0a
Delegated to: Masahiro Yamada
Headers show

Commit Message

Masahiro Yamada Oct. 8, 2016, 4:25 a.m. UTC 
For Electro-Magnetic Compatibility test.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/mach-uniphier/clk/pll-ld11.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index 8a4a748..7746deb 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -23,6 +23,7 @@  void uniphier_ld11_pll_init(void)
 	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
 	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
 	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
 
 	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
 	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);