From patchwork Mon Sep 26 03:34:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 674930 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sj91K4d1bz9s65 for ; Mon, 26 Sep 2016 13:48:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=O2T/wHwx; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9ADEBA780D; Mon, 26 Sep 2016 05:41:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VAaRtUPq_0ky; Mon, 26 Sep 2016 05:41:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9414BB38E8; Mon, 26 Sep 2016 05:37:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D3FDAB3894 for ; Mon, 26 Sep 2016 05:36:05 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eoX-SIClcctf for ; Mon, 26 Sep 2016 05:36:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-it0-f42.google.com (mail-it0-f42.google.com [209.85.214.42]) by theia.denx.de (Postfix) with ESMTPS id 1032FA776F for ; Mon, 26 Sep 2016 05:35:35 +0200 (CEST) Received: by mail-it0-f42.google.com with SMTP id r192so62677473ita.0 for ; Sun, 25 Sep 2016 20:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=DleALOXh70VrTdvOdPcOBMxIPHk6F2J0qHVXCQhKh8A=; b=O2T/wHwxMS2WzhUSK8TZDR7ciQPW8qQb8r09wwyDnNfl8VcDxGh3BIFx4PtyKyxwPG mm1txNbsaQfrzxVSj8Rh0tnn4Qv3CAI28b2+t/UjRrzEuEouF965/RIEX4IxSFGtDNAA sS0ZnVGG89oMIG2mNnOcDztDq/XYLxV4ltHTSBQj/Nf+XVxCAR54+vCvp8+yrvrHpNl0 UST1fwhwJdBBGFzoYS+eUsiKbSjf7mqhIq2byZKvCsumRNDOvwZsjJxW6cc+Az816eYq vAdHbzuz37zCzldXSa+jAxTeWGZSOEMi6dO+KNCQZvG034kNHhO69wapzL0ZkTRwSXb/ Q8XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=DleALOXh70VrTdvOdPcOBMxIPHk6F2J0qHVXCQhKh8A=; b=khGOL31X1aIKmyQYtDR1+7mY05s+w01aZ0PNaHP5b8zpN7OtRbYgUxHx+60Y2tNtFX DN8vqvTBmHf3zn4IYfST8HPRBf6WadCKmY/C+d22XjEQ/jiBOMMs4h8pKFIDWFJ9fbsZ x3Mk5ZdAt2UiPWbnPDFYHyzzKTTKLFM0taPYgZXpSJjRAmNiSxOrJBep2eqAoblNtiSI 0hV4sbpgZzJ+aRNYCfXpI7fbsG/zYxj8FzeM0dCXos94qpmppJCV2VW226lJKeNRLpxe dy2zQ9N/Tj0tzcdXfW2dyeFZGnXyU+Zs55UXbeQgYFkgNxEaxnIznBHsC4zCSYx0oOyX 1tnw== X-Gm-Message-State: AA6/9Rl29Zy2+qvUp8+8TLdxz47c0JsPJ1S0MpWmV4jo9G6vM52jzwmis6JNfjTRWJp+ODw9 X-Received: by 10.36.217.133 with SMTP id p127mr15170481itg.7.1474860934251; Sun, 25 Sep 2016 20:35:34 -0700 (PDT) Received: from kaki.bld.corp.google.com ([2620:0:1005:12:61b7:f33c:9010:eb01]) by smtp.gmail.com with ESMTPSA id n133sm3176732ith.1.2016.09.25.20.35.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Sep 2016 20:35:29 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 362EC22345E; Sun, 25 Sep 2016 21:35:26 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Sun, 25 Sep 2016 21:34:22 -0600 Message-Id: <1474860866-16406-80-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1474860866-16406-1-git-send-email-sjg@chromium.org> References: <1474860866-16406-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH 79/82] x86: link: Set up device tree for SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass --- arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 9deb56c..fad9a11 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -26,12 +26,14 @@ cpus { #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc; cpu@0 { device_type = "cpu"; compatible = "intel,core-gen3"; reg = <0>; intel,apic-id = <0>; + u-boot,dm-pre-reloc; }; cpu@1 { @@ -39,6 +41,7 @@ compatible = "intel,core-gen3"; reg = <1>; intel,apic-id = <1>; + u-boot,dm-pre-reloc; }; cpu@2 { @@ -46,6 +49,7 @@ compatible = "intel,core-gen3"; reg = <2>; intel,apic-id = <2>; + u-boot,dm-pre-reloc; }; cpu@3 { @@ -53,6 +57,7 @@ compatible = "intel,core-gen3"; reg = <3>; intel,apic-id = <3>; + u-boot,dm-pre-reloc; }; }; @@ -229,14 +234,16 @@ northbridge@0,0 { reg = <0x00000000 0 0 0 0>; + u-boot,dm-pre-reloc; compatible = "intel,bd82x6x-northbridge"; board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>, <&gpio_b 11 0>, <&gpio_a 10 0>; - u-boot,dm-pre-reloc; spd { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; elpida_4Gb_1600_x16 { + u-boot,dm-pre-reloc; reg = <0>; data = [92 10 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 @@ -272,6 +279,7 @@ 00 00 00 00 00 00 00 00]; }; samsung_4Gb_1600_1.35v_x16 { + u-boot,dm-pre-reloc; reg = <1>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 @@ -391,9 +399,11 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + u-boot,dm-pre-reloc; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; + u-boot,dm-pre-reloc; reg = <0>; compatible = "winbond,w25q64", "spi-flash"; @@ -401,6 +411,7 @@ rw-mrc-cache { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; + u-boot,dm-pre-reloc; }; }; }; @@ -478,7 +489,9 @@ }; microcode { + u-boot,dm-pre-reloc; update@0 { + u-boot,dm-pre-reloc; #include "microcode/m12306a9_0000001b.dtsi" }; };