From patchwork Mon Aug 13 14:18:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 176952 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 00B882C0093 for ; Tue, 14 Aug 2012 00:12:58 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A4EE28091; Mon, 13 Aug 2012 16:12:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id g9a5PUZ9Mu7s; Mon, 13 Aug 2012 16:12:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F97228088; Mon, 13 Aug 2012 16:12:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A3A9D28088 for ; Mon, 13 Aug 2012 16:12:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id w-g6GukjE4kb for ; Mon, 13 Aug 2012 16:12:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta-11.w4a.fr [178.33.204.86]) by theia.denx.de (Postfix) with ESMTP id E244628085 for ; Mon, 13 Aug 2012 16:12:46 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id B216546029; Mon, 13 Aug 2012 16:17:32 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gyKmwuu3oltY; Mon, 13 Aug 2012 16:17:32 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 23D8546012; Mon, 13 Aug 2012 16:17:32 +0200 (CEST) Date: Mon, 13 Aug 2012 16:18:04 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: u-boot@lists.denx.de Message-ID: <1473596284.2361385.1344867484728.JavaMail.root@advansee.com> In-Reply-To: <5026D55C.50906@denx.de> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Cc: Andy Fleming , Kim Phillips Subject: [U-Boot] [PATCH 1/2] imx: Define architecture identifier X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Define ARCH_IMX for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Andy Fleming Cc: Kim Phillips --- .../arch/arm/include/asm/arch-imx/imx-regs.h | 3 +++ .../arch/arm/include/asm/arch-mx25/imx-regs.h | 2 ++ .../arch/arm/include/asm/arch-mx27/imx-regs.h | 2 ++ .../arch/arm/include/asm/arch-mx31/imx-regs.h | 2 ++ .../arch/arm/include/asm/arch-mx35/imx-regs.h | 2 ++ .../arch/arm/include/asm/arch-mx5/imx-regs.h | 2 ++ .../arch/arm/include/asm/arch-mx6/imx-regs.h | 2 ++ 7 files changed, 15 insertions(+) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-imx/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-imx/imx-regs.h index ec94ba9..35ebf82 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-imx/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-imx/imx-regs.h @@ -1,5 +1,8 @@ #ifndef _IMX_REGS_H #define _IMX_REGS_H + +#define ARCH_IMX + /* ------------------------------------------------------------------------ * Motorola IMX system registers * ------------------------------------------------------------------------ diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx25/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx25/imx-regs.h index cf925d7..3e48fe9 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx25/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -172,6 +172,8 @@ struct aips_regs { #endif +#define ARCH_IMX + /* AIPS 1 */ #define IMX_AIPS1_BASE (0x43F00000) #define IMX_MAX_BASE (0x43F04000) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx27/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx27/imx-regs.h index ced5b2a..d095c17 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx27/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -217,6 +217,8 @@ struct fuse_bank0_regs { #endif +#define ARCH_IMX + #define IMX_IO_BASE 0x10000000 #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h index 7ddbbd6..59fb7c4 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -541,6 +541,8 @@ struct esdc_regs { #endif +#define ARCH_IMX + #define __REG(x) (*((volatile u32 *)(x))) #define __REG16(x) (*((volatile u16 *)(x))) #define __REG8(x) (*((volatile u8 *)(x))) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 3146006..d80d52f 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -25,6 +25,8 @@ #ifndef __ASM_ARCH_MX35_H #define __ASM_ARCH_MX35_H +#define ARCH_IMX + /* * IRAM */ diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/imx-regs.h index 7f66b61..24daef0 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -23,6 +23,8 @@ #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ #define __ASM_ARCH_MX5_IMX_REGS_H__ +#define ARCH_IMX + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx6/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d77603..1edfc25 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx6/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -19,6 +19,8 @@ #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ #define __ASM_ARCH_MX6_IMX_REGS_H__ +#define ARCH_IMX + #define CONFIG_SYS_CACHELINE_SIZE 32 #define ROMCP_ARB_BASE_ADDR 0x00000000