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[U-Boot] armv8: fsl-layerscape: Update ddr erratum a008336

Message ID 1472207439-3275-1-git-send-email-Shengzhou.Liu@nxp.com
State Accepted
Commit 1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f
Delegated to: York Sun
Headers show

Commit Message

Shengzhou Liu Aug. 26, 2016, 10:30 a.m. UTC 
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

York Sun Sept. 20, 2016, 5:59 p.m. UTC | #1 
On 08/26/2016 03:42 AM, Shengzhou Liu wrote:
> DDR erratum A008336 only applies to DDR controller v5.2.0.
> DDR controller v5.2.1 already has default 0x43b30002 in
> EDDRTQCR1 register for optimal performance.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
> ---


Applied to fsl-qoriq master. Awaiting upstream. Thanks.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..28928b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -58,11 +58,13 @@  static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-	out_le32(eddrtqcr1, 0x63b30002);
+	if (fsl_ddr_get_version(0) == 0x50200)
+		out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-	out_le32(eddrtqcr1, 0x63b30002);
+	if (fsl_ddr_get_version(0) == 0x50200)
+		out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #endif
 }