| Message ID | 1470680002-16354-2-git-send-email-vz@mleia.com |
|---|---|
| State | Accepted |
| Commit | ee47c4cb2b3413b3ee0edd2207de46d715b2628c |
| Delegated to: | Nobuhiro Iwamatsu |
| Headers | show |
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index e1ee970..b3e5fd5 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -97,7 +97,7 @@ void flush_dcache_range(unsigned long start, unsigned long end) start &= ~(L1_CACHE_BYTES - 1); for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ + asm volatile ("ocbp %0" : /* no output */ : "m" (__m(v))); } }
In common usecases flush_cache() assumes both cache invalidation and write-back to memory, thus in flush_dcache_range() implementation change SH4 cache write-back only instruction 'ocbwb' with cache purge instruction 'ocbp', according to the User's Manual there should be no performance penalty for that. Note that under circumstances only cache invalidation is expected from flush_cache() call, in these occasional cases the current version of flush_cache() works, which is a wrapper over invalidate_dcache_range() at the moment, this will be fixed in the following change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/sh/cpu/sh4/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)