From patchwork Fri Jul 22 21:51:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 651775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rx4Bj6tBGz9sdg for ; Sat, 23 Jul 2016 07:52:45 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34903B38C1; Fri, 22 Jul 2016 23:52:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O-7g9hpz7t3c; Fri, 22 Jul 2016 23:52:19 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E30BB38B6; Fri, 22 Jul 2016 23:51:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9FC94A76F7 for ; Fri, 22 Jul 2016 23:51:33 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tYJ6Hl84Wdc8 for ; Fri, 22 Jul 2016 23:51:33 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gloria.sntech.de (gloria.sntech.de [95.129.55.99]) by theia.denx.de (Postfix) with ESMTPS id 6B2E8B3899 for ; Fri, 22 Jul 2016 23:51:32 +0200 (CEST) Received: from ip9234aa3a.dynamic.kabel-deutschland.de ([146.52.170.58] helo=diego.sntech) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1bQiLw-0008C6-Oa; Fri, 22 Jul 2016 23:51:32 +0200 From: Heiko Stuebner To: sjg@chromium.org Date: Fri, 22 Jul 2016 23:51:11 +0200 Message-Id: <1469224272-17220-8-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1469224272-17220-1-git-send-email-heiko@sntech.de> References: <1469224272-17220-1-git-send-email-heiko@sntech.de> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 7/8] rockchip: rk3188: add core support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- arch/arm/dts/rk3188.dtsi | 631 ++++++++++++++++++++++++++ arch/arm/dts/rk3xxx.dtsi | 431 ++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 11 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3188/Kconfig | 9 + arch/arm/mach-rockchip/rk3188/Makefile | 9 + arch/arm/mach-rockchip/rk3188/clk_rk3188.c | 17 + arch/arm/mach-rockchip/rk3188/reset_rk3188.c | 47 ++ arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 24 + include/configs/rk3188_common.h | 95 ++++ tools/rkcommon.c | 1 + 11 files changed, 1276 insertions(+) create mode 100644 arch/arm/dts/rk3188.dtsi create mode 100644 arch/arm/dts/rk3xxx.dtsi create mode 100644 arch/arm/mach-rockchip/rk3188/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3188/Makefile create mode 100644 arch/arm/mach-rockchip/rk3188/clk_rk3188.c create mode 100644 arch/arm/mach-rockchip/rk3188/reset_rk3188.c create mode 100644 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c create mode 100644 include/configs/rk3188_common.h diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi new file mode 100644 index 0000000..ef1b962 --- /dev/null +++ b/arch/arm/dts/rk3188.dtsi @@ -0,0 +1,631 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3188"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x3>; + }; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + spdif: sound@1011e000 { + compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; + reg = <0x1011e000 0x2000>; + #sound-dai-cells = <0>; + clock-names = "hclk", "mclk"; + clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; + dmas = <&dmac1_s 8>; + dma-names = "tx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rockchip-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + usbphy: phy { + compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + #phy-cells = <0>; + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy1: usb-phy@11c { + #phy-cells = <0>; + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3188-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = ; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = ; + }; + + emmc_rst: emmc-rst { + rockchip,pins = ; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = , /* tx_en */ + , /* txd1 */ + , /* txd0 */ + , /* rxd0 */ + , /* rxd1 */ + , /* mac_clk */ + , /* rx_err */ + ; /* crs_dvalid */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = , + ; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = , + ; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = , + ; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = , + ; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = , + ; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = , + ; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = ; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = ; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = ; + }; + spi0_tx: spi0-tx { + rockchip,pins = ; + }; + spi0_rx: spi0-rx { + rockchip,pins = ; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = ; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = ; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = ; + }; + spi1_rx: spi1-rx { + rockchip,pins = ; + }; + spi1_tx: spi1-tx { + rockchip,pins = ; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = ; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + }; + + uart1_cts: uart1-cts { + rockchip,pins = ; + }; + + uart1_rts: uart1-rts { + rockchip,pins = ; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; + }; + + uart3_cts: uart3-cts { + rockchip,pins = ; + }; + + uart3_rts: uart3-rts { + rockchip,pins = ; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = ; + }; + + sd0_cd: sd0-cd { + rockchip,pins = ; + }; + + sd0_wp: sd0-wp { + rockchip,pins = ; + }; + + sd0_pwr: sd0-pwr { + rockchip,pins = ; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = ; + }; + + sd1_cd: sd1-cd { + rockchip,pins = ; + }; + + sd1_wp: sd1-wp { + rockchip,pins = ; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = ; + }; + }; + }; +}; + +&emac { + compatible = "rockchip,rk3188-emac"; +}; + +&global_timer { + interrupts = ; +}; + +&grf { + compatible = "rockchip,rk3188-grf", "syscon"; +}; + +&local_timer { + interrupts = ; +}; + +&i2c0 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&pmu { + compatible = "rockchip,rk3188-pmu", "syscon"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&wdt { + compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; +}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi new file mode 100644 index 0000000..15a62d9 --- /dev/null +++ b/arch/arm/dts/rk3xxx.dtsi @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + ethernet0 = &emac; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + mshc0 = &emmc; + mshc1 = &mmc0; + mshc2 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + clock-output-names = "xin24m"; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + global_timer: global-timer@1013c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1013c200 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + local_timer: local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + status = "disabled"; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + phys = <&usbphy1>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + emac: ethernet@10204000 { + compatible = "snps,arc-emac"; + reg = <0x10204000 0x3c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; + clock-names = "hclk", "macref"; + max-speed = <100>; + phy-mode = "rmii"; + + status = "disabled"; + }; + + mmc0: dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + + mmc1: dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x1021c000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; + reg = <0x20004000 0x100>; + }; + + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + + i2c0: i2c@2002d000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002d000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + + status = "disabled"; + }; + + i2c1: i2c@2002f000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002f000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C1>; + clock-names = "i2c"; + + status = "disabled"; + }; + + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + wdt: watchdog@2004c000 { + compatible = "snps,dw-wdt"; + reg = <0x2004c000 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + i2c2: i2c@20056000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C2>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c3: i2c@2005a000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C3>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c4: i2c@2005e000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C4>; + clock-names = "i2c"; + + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-frequency = <24000000>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + status = "disabled"; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi@20070000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20070000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@20074000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20074000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; +}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 362dc28..c47e16c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,16 @@ config ROCKCHIP_RK3036 select SUPPORT_SPL select SPL +config ROCKCHIP_RK3188 + bool "Support Rockchip RK3188" + select CPU_V7 + help + The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 @@ -43,6 +53,7 @@ config ROCKCHIP_RK3399 select ARM64 source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 722b582..cabc91b 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,4 +15,5 @@ ifndef CONFIG_ARM64 obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig new file mode 100644 index 0000000..7ec9364 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -0,0 +1,9 @@ +if ROCKCHIP_RK3188 + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +endif diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile new file mode 100644 index 0000000..2ffbd15 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk_rk3188.o +obj-y += reset_rk3188.o +obj-y += syscon_rk3188.o diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c new file mode 100644 index 0000000..902524f --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3188_cru), devp); +} diff --git a/arch/arm/mach-rockchip/rk3188/reset_rk3188.c b/arch/arm/mach-rockchip/rk3188/reset_rk3188.c new file mode 100644 index 0000000..65a1465 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/reset_rk3188.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3188_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(RK_CLRBITS(0xffff), &cru->cru_mode_con); + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(RK_CLRBITS(0xffff), &cru->cru_mode_con); + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3188_sysreset = { + .request = rk3188_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3188) = { + .name = "rk3188_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3188_sysreset, +}; diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c new file mode 100644 index 0000000..05c36bd --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id rk3188_syscon_ids[] = { + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC }, + { .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3188-pmu", .data = ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3188) = { + .name = "rk3188_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids, +}; diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h new file mode 100644 index 0000000..7bd5b63 --- /dev/null +++ b/include/configs/rk3188_common.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3188_COMMON_H +#define __CONFIG_RK3188_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#include + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE 0x8000 - 0x800 +#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" + +#define CONFIG_ROCKCHIP_COMMON + +/* #define CONFIG_SILENT_CONSOLE +#ifndef CONFIG_SPL_BUILD +# define CONFIG_SYS_CONSOLE_IS_IN_ENV +# define CONFIG_CONSOLE_MUX +#endif */ + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +#include + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include + +/* Linux fails to load the fdt if it's loaded above 512M on rk3188 boards, so + * limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x7fffffff\0" \ + "initrd_high=0x7fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 0a072aa..0f38b15 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -55,6 +55,7 @@ struct spl_info { static struct spl_info spl_infos[] = { { "rk3036", "RK30", 0x1000 }, + { "rk3188", "RK31", 0x8000 - 0x800 }, { "rk3288", "RK32", 0x8000 }, { "rk3399", "RK33", 0x20000 }, };