| Message ID | 1469100512-5467-2-git-send-email-Russ.Dill@ti.com |
|---|---|
| State | Accepted |
| Commit | 3325b06556b78a2afdaaa781765b505f7d1f8ae4 |
| Delegated to: | Tom Rini |
| Headers | show |
On Thu, Jul 21, 2016 at 04:28:31AM -0700, Russ Dill wrote: > The delay needs to be before the write to ref_ctrl register > which initiates refreshes. An improper initialization sequence > generates an L3 noc error. > > Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
On Thu, Jul 21, 2016 at 04:28:31AM -0700, Russ Dill wrote: > The delay needs to be before the write to ref_ctrl register > which initiates refreshes. An improper initialization sequence > generates an L3 noc error. > > Signed-off-by: Russ Dill <Russ.Dill@ti.com> > Reviewed-by: Tom Rini <trini@konsulko.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 888cf1f..ef1fc4d 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -120,12 +120,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); /* Perform hardware leveling for DDR3 */ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { - udelay(1000); writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
The delay needs to be before the write to ref_ctrl register which initiates refreshes. An improper initialization sequence generates an L3 noc error. Signed-off-by: Russ Dill <Russ.Dill@ti.com> --- arch/arm/cpu/armv7/am33xx/ddr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)