From patchwork Mon Jul 18 09:00:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 649406 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rtHGb5NSHz9ryT for ; Mon, 18 Jul 2016 19:01:27 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B963FA7514; Mon, 18 Jul 2016 11:01:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zzmxMRIzdJuF; Mon, 18 Jul 2016 11:01:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37EDCA74E9; Mon, 18 Jul 2016 11:01:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 198D6A74E9 for ; Mon, 18 Jul 2016 11:01:21 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uhr2WL3cWYek for ; Mon, 18 Jul 2016 11:01:21 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.136]) by theia.denx.de (Postfix) with ESMTPS id 3B3C3A74D6 for ; Mon, 18 Jul 2016 11:01:16 +0200 (CEST) Received: from kever.yang?rock-chips.com (unknown [192.168.167.192]) by regular1.263xmail.com (Postfix) with SMTP id 0531D8E; Mon, 18 Jul 2016 17:01:11 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id E641D3BE; Mon, 18 Jul 2016 17:01:08 +0800 (CST) X-RL-SENDER: kever.yang@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: kever.yang@rock-chips.com X-UNIQUE-TAG: <6b7c8d98cd117a6d94f0b43a5b6f7201> X-ATTACHMENT-NUM: 0 X-SENDER: yk@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 29356YH6L0A; Mon, 18 Jul 2016 17:01:10 +0800 (CST) From: Kever Yang To: sjg@chromium.org Date: Mon, 18 Jul 2016 17:00:58 +0800 Message-Id: <1468832458-28655-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 Cc: hl@rock-chips.com, jeffy.chen@rock-chips.com, Pantelis Antoniou , u-boot@lists.denx.de, eddie.cai@rock-chips.com Subject: [U-Boot] [PATCH] mmc: rockchip: add SDHCI driver support for rockchip soc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Rockchip rk3399 using arasan sdhci-5.1 controller. This patch add the controller support to enable mmc device with full driver-model support, tested on rk3399 evb board. According to my test result, this driver should be OK, the command "part list mmc 0" can result in a right output, but all the mmc command failed like this: => mmc info No MMC device available Command failed, result=1 The result of get_mmc_num in cmd/mmc.c is always 0? Signed-off-by: Kever Yang Acked-by: Simon Glass --- drivers/mmc/Kconfig | 6 +++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_sdhci.c | 93 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/mmc/rockchip_sdhci.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index e0adb9b..dc8f2b6 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -61,6 +61,12 @@ config ZYNQ_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform +config ROCKCHIP_SDHCI + bool "Arasan SDHCI controller for Rockchip support" + depends on DM_MMC && BLK && DM_MMC_OPS + help + Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform + config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index b44a12e..18351fb 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c new file mode 100644 index 0000000..023c29b --- /dev/null +++ b/drivers/mmc/rockchip_sdhci.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Rockchip SD Host Controller Interface + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* 400KHz is max freq for card ID etc. Use that as min */ +#define EMMC_MIN_FREQ 400000 + +struct rockchip_sdhc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct rockchip_sdhc { + struct sdhci_host host; + void *base; +}; + +static int arasan_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + struct rockchip_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + int ret; + u32 caps; + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width, + caps, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, EMMC_MIN_FREQ, + host->version, host->quirks, 0); + + host->mmc = &plat->mmc; + if (ret) + return ret; + host->mmc->priv = &prv->host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + return sdhci_probe(dev); +} + +static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + + host->name = dev->name; + host->ioaddr = dev_get_addr_ptr(dev); + + return 0; +} + +static int rockchip_sdhci_bind(struct udevice *dev) +{ + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id arasan_sdhci_ids[] = { + { .compatible = "arasan,sdhci-5.1" }, + { } +}; + +U_BOOT_DRIVER(arasan_sdhci_drv) = { + .name = "arasan_sdhci", + .id = UCLASS_MMC, + .of_match = arasan_sdhci_ids, + .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = rockchip_sdhci_bind, + .probe = arasan_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), + .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), +};