From patchwork Wed Jul 6 09:34:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Ziyuan X-Patchwork-Id: 645188 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rkwb80dVdz9sBm for ; Wed, 6 Jul 2016 19:35:16 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AAB094BDE9; Wed, 6 Jul 2016 11:35:01 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xDAdONFLVOTh; Wed, 6 Jul 2016 11:35:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A00DCA74F1; Wed, 6 Jul 2016 11:34:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5145CA74E0 for ; Wed, 6 Jul 2016 11:34:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PcTWAXTeAa-m for ; Wed, 6 Jul 2016 11:34:54 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.138]) by theia.denx.de (Postfix) with ESMTPS id 18AC1A74FF for ; Wed, 6 Jul 2016 11:34:44 +0200 (CEST) Received: from xzy.xu?rock-chips.com (unknown [192.168.167.11]) by regular1.263xmail.com (Postfix) with SMTP id 541147A02; Wed, 6 Jul 2016 17:34:40 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 6D1F8631B; Wed, 6 Jul 2016 17:34:34 +0800 (CST) X-RL-SENDER: xzy.xu@rock-chips.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: xzy.xu@rock-chips.com X-UNIQUE-TAG: <977e0a0d0cbd292326715f3c142d2dd0> X-ATTACHMENT-NUM: 0 X-SENDER: xzy.xu@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith SMTP id 18328W121W4; Wed, 06 Jul 2016 17:34:39 +0800 (CST) From: Ziyuan Xu To: sjg@chromium.org, marex@denx.de Date: Wed, 6 Jul 2016 17:34:22 +0800 Message-Id: <1467797663-16276-4-git-send-email-xzy.xu@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467797663-16276-1-git-send-email-xzy.xu@rock-chips.com> References: <1467797663-16276-1-git-send-email-xzy.xu@rock-chips.com> Cc: hl@rock-chips.com, frank.wang@rock-chips.com, u-boot@lists.denx.de, eddie.cai@rock-chips.com, william.wu@rock-chips.com Subject: [U-Boot] [PATCH v3 3/4] rockchip: rk3288: add fastboot support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Xu Ziyuan Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu --- Changes in v3: - Achieve UOC_CON_OFFSET physical address from DT Changes in v2: - Achieve the regs_phy from DT - Update comments a little arch/arm/dts/rk3288.dtsi | 1 + arch/arm/mach-rockchip/board.c | 60 +++++++++++++++++++++++++++++++++++++++++ include/configs/rk3288_common.h | 26 ++++++++++++++++++ 3 files changed, 87 insertions(+) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 3dab0fc..bcf051a 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -454,6 +454,7 @@ interrupts = ; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 816540e..56e3c31 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -52,6 +52,66 @@ void lowlevel_init(void) { } +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include +#include + +static struct dwc2_plat_otg_data rk3288_otg_data; + +int board_usb_init(int index, enum usb_init_type init) +{ + int offset; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + u32 grf_phy_offset; + + /* find the usb_otg node */ + offset = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (offset > 0) { + mode = fdt_getprop(blob, offset, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + offset = fdt_node_offset_by_compatible(blob, offset, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, offset, "reg"); + + offset = fdtdec_lookup_phandle(blob, offset, "phys"); + if (offset <= 0) { + debug("Not found usb phy device\n"); + return -ENODEV; + } + grf_phy_offset = fdtdec_get_addr(blob, offset, "reg"); + + /* find the grf node */ + offset = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-grf"); + if (offset <= 0) { + debug("Not found grf device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_phy = grf_phy_offset + + fdtdec_get_addr(blob, offset, "reg"); + + return dwc2_udc_probe(&rk3288_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 9d50d83..94fd13f 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -80,6 +80,32 @@ #define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB_SYNO_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ +/* stroe safely fastboot buffer data to the middle of bank */ +#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ + + SDRAM_BANK_SIZE / 2) +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a + +/* Enable gpt partition table */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + #ifndef CONFIG_SPL_BUILD #include