From patchwork Wed Jul 6 09:34:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Ziyuan X-Patchwork-Id: 645186 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rkwZk3wYdz9sBm for ; Wed, 6 Jul 2016 19:34:54 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0826C4BDBD; Wed, 6 Jul 2016 11:34:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x5MRm1WX1PfO; Wed, 6 Jul 2016 11:34:48 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 23052A750E; Wed, 6 Jul 2016 11:34:45 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 88ACB4BA16 for ; Wed, 6 Jul 2016 11:34:40 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DnAEJG-NRj6L for ; Wed, 6 Jul 2016 11:34:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.134]) by theia.denx.de (Postfix) with ESMTPS id 12C8D4A039 for ; Wed, 6 Jul 2016 11:34:37 +0200 (CEST) Received: from xzy.xu?rock-chips.com (unknown [192.168.167.11]) by regular1.263xmail.com (Postfix) with SMTP id B5C549154; Wed, 6 Jul 2016 17:34:31 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 98D6F6356; Wed, 6 Jul 2016 17:34:29 +0800 (CST) X-RL-SENDER: xzy.xu@rock-chips.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: xzy.xu@rock-chips.com X-UNIQUE-TAG: <97cb76713a8bfc3c7eab1220cc95ceae> X-ATTACHMENT-NUM: 0 X-SENDER: xzy.xu@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith SMTP id 18328K2340N; Wed, 06 Jul 2016 17:34:31 +0800 (CST) From: Ziyuan Xu To: sjg@chromium.org, marex@denx.de Date: Wed, 6 Jul 2016 17:34:20 +0800 Message-Id: <1467797663-16276-2-git-send-email-xzy.xu@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467797663-16276-1-git-send-email-xzy.xu@rock-chips.com> References: <1467797663-16276-1-git-send-email-xzy.xu@rock-chips.com> Cc: hl@rock-chips.com, frank.wang@rock-chips.com, u-boot@lists.denx.de, eddie.cai@rock-chips.com, william.wu@rock-chips.com Subject: [U-Boot] [PATCH v3 1/4] usb: rockchip-phy: implement USB2.0 phy control for Synopsys X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Xu Ziyuan So far, Rockchip SoCs have two kinds of USB2.0 phy, like Synopsys and Innosilicon. This patch applys dwc2 usb driver framework to implement phy_init and phy_off for Synopsys phy on Rockchip platform. Signed-off-by: Ziyuan Xu --- Changes in v3: - Make UOC_CON registers to be unfixed which should be got from DT Changes in v2: - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c - Rework the behaviour in otg_phy_init() and otg_phy_off() drivers/usb/phy/Makefile | 1 + drivers/usb/phy/rockchip_usb_syno_phy.c | 47 +++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 93d147e..8002a18 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TWL4030_USB) += twl4030.o obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o +obj-$(CONFIG_ROCKCHIP_USB_SYNO_PHY) += rockchip_usb_syno_phy.o diff --git a/drivers/usb/phy/rockchip_usb_syno_phy.c b/drivers/usb/phy/rockchip_usb_syno_phy.c new file mode 100644 index 0000000..ab049e1 --- /dev/null +++ b/drivers/usb/phy/rockchip_usb_syno_phy.c @@ -0,0 +1,47 @@ +/* + * Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "../gadget/dwc2_udc_otg_priv.h" + +#define UOC_CON(x) ((x) * 0x4) + +#define RESET_WRITE_ENA BIT(28) +#define PORT_RESET BIT(12) +#define PORT_NORMAL (0 << 12) + +#define SOFT_CTRL_WRITE_ENA BIT(18) +#define SOFT_CTRL_ENABLE BIT(2) + +#define SUSPEND_SETTING 0x2A +#define SUSPEND_WRITE_ENA (0x3f << 16) + + +void otg_phy_init(struct dwc2_udc *dev) +{ + /* disable software control */ + writel(SOFT_CTRL_WRITE_ENA | (0 << 2), + dev->pdata->regs_phy + UOC_CON(2)); + /* reset otg port */ + writel(RESET_WRITE_ENA | PORT_RESET, + dev->pdata->regs_phy + UOC_CON(0)); + mdelay(1); + writel(RESET_WRITE_ENA | PORT_NORMAL, + dev->pdata->regs_phy + UOC_CON(0)); + udelay(1); +} + +void otg_phy_off(struct dwc2_udc *dev) +{ + /* enable software control */ + writel(SOFT_CTRL_WRITE_ENA | SOFT_CTRL_ENABLE, + dev->pdata->regs_phy + UOC_CON(2)); + /* enter suspend */ + writel(SUSPEND_WRITE_ENA | SUSPEND_SETTING, + dev->pdata->regs_phy + UOC_CON(3)); +}