From patchwork Mon Jun 6 09:44:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siva Durga Prasad Paladugu X-Patchwork-Id: 630758 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rNVFt6FH4z9snm for ; Mon, 6 Jun 2016 19:46:26 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6CB1AA7564; Mon, 6 Jun 2016 11:46:25 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BKeymEd5iLpP; Mon, 6 Jun 2016 11:46:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2F001A7530; Mon, 6 Jun 2016 11:45:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9D07AA74EE for ; Mon, 6 Jun 2016 11:45:14 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DCpbjH5AySDi for ; Mon, 6 Jun 2016 11:45:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0053.outbound.protection.outlook.com [104.47.38.53]) by theia.denx.de (Postfix) with ESMTPS id 3B68AA7514 for ; Mon, 6 Jun 2016 11:45:07 +0200 (CEST) Received: from BL2NAM02FT013.eop-nam02.prod.protection.outlook.com (10.152.76.59) by BL2NAM02HT093.eop-nam02.prod.protection.outlook.com (10.152.77.196) with Microsoft SMTP Server (TLS) id 15.1.511.7; Mon, 6 Jun 2016 09:45:03 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; lists.denx.de; dkim=none (message not signed) header.d=none;lists.denx.de; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by BL2NAM02FT013.mail.protection.outlook.com (10.152.77.19) with Microsoft SMTP Server (TLS) id 15.1.511.7 via Frontend Transport; Mon, 6 Jun 2016 09:45:03 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:41223 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1b9r5g-0003rg-Gb; Mon, 06 Jun 2016 02:45:00 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1b9r5h-0003Z0-U0; Mon, 06 Jun 2016 02:45:02 -0700 Received: from xsj-pvapsmtp01 (mailman.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u569j0RW032563; Mon, 6 Jun 2016 02:45:00 -0700 Received: from [172.23.146.171] (helo=xhdl3763.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1b9r5f-0003Vr-Rn; Mon, 06 Jun 2016 02:45:00 -0700 Received: by xhdl3763.xilinx.com (Postfix, from userid 13899) id 1500C2CE02C3; Mon, 6 Jun 2016 15:14:59 +0530 (IST) From: Siva Durga Prasad Paladugu To: Date: Mon, 6 Jun 2016 15:14:47 +0530 Message-ID: <1465206294-38490-2-git-send-email-sivadur@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1465206294-38490-1-git-send-email-sivadur@xilinx.com> References: <1465206294-38490-1-git-send-email-sivadur@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22374.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(19580395003)(45336002)(110136002)(19580405001)(107886002)(106466001)(46386002)(103686003)(47776003)(189998001)(52956003)(33646002)(87936001)(50986999)(42186005)(5003940100001)(76176999)(86362001)(63266004)(36386004)(229853001)(2351001)(50466002)(586003)(48376002)(92566002)(36756003)(11100500001)(4001430100002)(8936002)(4326007)(50226002)(6806005)(90966002)(2906002)(5008740100001)(81156014)(81166006)(2950100001)(8676002)(107986001)(5001870100001); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2NAM02HT093; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; PTR:xapps1.xilinx.com,unknown-60-100.xilinx.com; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: d0541973-43bf-45a4-6bd2-08d38def3c08 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(8251501002); SRVR:BL2NAM02HT093; X-Microsoft-Antispam-PRVS: <4c0d1e61ae8848c3ba73a81f803d72df@BL2NAM02HT093.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(13024025)(13018025)(13023025)(13015025)(8121501046)(5005006)(13017025)(10201501046)(3002001)(6055026); SRVR:BL2NAM02HT093; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT093; X-Forefront-PRVS: 096507C068 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2016 09:45:03.0757 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT093 Cc: michals@xilinx.com, Siva Durga Prasad Paladugu Subject: [U-Boot] [PATCH 2/9] spi: zynq_qspi: Add support of Dual parallel and Dual stacked modes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add Dual parallel and dual stacked supports for zynq qspi driver. The is-dual property defines the dual parallel mode and num-cs, numbere of chip selects defines dual stacked mode if its value is 2 Signed-off-by: Siva Durga Prasad Paladugu --- drivers/spi/zynq_qspi.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 47 insertions(+), 0 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index e636244..44057ba 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -52,6 +52,10 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif +#define ZYNQ_QSPI_LCR_TWO_MEM_MASK BIT(30) /* QSPI Enable Bit Mask */ +#define ZYNQ_QSPI_LCR_SEP_BUS_MASK BIT(29) /* QSPI Enable Bit Mask */ +#define ZYNQ_QSPI_LCR_U_PAGE BIT(28) /* QSPI Upper memory set */ + /* zynq qspi register set */ struct zynq_qspi_regs { u32 cr; /* 0x00 */ @@ -96,6 +100,8 @@ struct zynq_qspi_priv { int bytes_to_transfer; int bytes_to_receive; unsigned int is_inst; + unsigned int is_dual; + unsigned int u_page; unsigned cs_change:1; }; @@ -154,6 +160,14 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; writel(confr, ®s->lqspicfg); + if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) + writel(ZYNQ_QSPI_LCR_TWO_MEM_MASK | + ZYNQ_QSPI_LCR_SEP_BUS_MASK, + ®s->lqspicfg); + else if (priv->is_dual == SF_DUAL_STACKED_FLASH) + writel(ZYNQ_QSPI_LCR_TWO_MEM_MASK, + ®s->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); } @@ -161,7 +175,9 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) static int zynq_qspi_child_pre_probe(struct udevice *bus) { struct spi_slave *slave = dev_get_parent_priv(bus); + struct zynq_qspi_priv *priv = dev_get_priv(bus->parent); + slave->option = priv->is_dual; slave->mode_rx = QUAD_OUTPUT_FAST; slave->mode = SPI_TX_QUAD; slave->no_all_quad = 1; @@ -173,10 +189,23 @@ static int zynq_qspi_probe(struct udevice *bus) { struct zynq_qspi_platdata *plat = dev_get_platdata(bus); struct zynq_qspi_priv *priv = dev_get_priv(bus); + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + u8 is_dual = 0; + u8 num_cs = 0; priv->regs = plat->regs; priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; + is_dual = fdtdec_get_int(blob, node, "is-dual", 0); + if (is_dual) { + priv->is_dual = SF_DUAL_PARALLEL_FLASH; + } else { + num_cs = fdtdec_get_int(blob, node, "num-cs", 1); + if (num_cs == 2) + priv->is_dual = SF_DUAL_STACKED_FLASH; + } + /* init the zynq spi hw */ zynq_qspi_init_hw(priv); @@ -437,6 +466,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) */ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) { + static u8 current_u_page; u32 data = 0; struct zynq_qspi_regs *regs = priv->regs; @@ -446,6 +476,18 @@ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) priv->bytes_to_transfer = priv->len; priv->bytes_to_receive = priv->len; + if (priv->is_inst && (priv->is_dual == SF_DUAL_STACKED_FLASH) && + (current_u_page != priv->u_page)) { + if (priv->u_page) + writel(ZYNQ_QSPI_LCR_TWO_MEM_MASK | + ZYNQ_QSPI_LCR_U_PAGE, + ®s->lqspicfg); + else + writel(ZYNQ_QSPI_LCR_TWO_MEM_MASK, + ®s->lqspicfg); + current_u_page = priv->u_page; + } + if (priv->len < 4) zynq_qspi_fill_tx_fifo(priv, priv->len); else @@ -555,6 +597,11 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, else priv->cs_change = 0; + if (flags & SPI_XFER_U_PAGE) + priv->u_page = 1; + else + priv->u_page = 0; + zynq_qspi_transfer(priv); return 0;