From patchwork Thu May 26 04:21:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenyou Yang X-Patchwork-Id: 626542 X-Patchwork-Delegate: andreas.biessmann@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rFbmr1GX3z9t3x for ; Thu, 26 May 2016 14:30:52 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 36D00A767C; Thu, 26 May 2016 06:30:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9paNL2WYEBJR; Thu, 26 May 2016 06:30:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A831A75CA; Thu, 26 May 2016 06:30:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 68BE5A75CA for ; Thu, 26 May 2016 06:30:46 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gQ_aeH_SWdPl for ; Thu, 26 May 2016 06:30:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.243]) by theia.denx.de (Postfix) with ESMTPS id 25F0EA74EE for ; Thu, 26 May 2016 06:30:42 +0200 (CEST) Received: from apsmtp01.atmel.com (10.168.254.31) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Thu, 26 May 2016 06:30:37 +0200 Received: from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com (10.168.254.31) with Microsoft SMTP Server id 14.3.235.1; Thu, 26 May 2016 12:34:15 +0800 From: Wenyou Yang To: U-Boot Mailing List Date: Thu, 26 May 2016 12:21:41 +0800 Message-ID: <1464236504-12606-3-git-send-email-wenyou.yang@atmel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1464236504-12606-1-git-send-email-wenyou.yang@atmel.com> References: <1464236504-12606-1-git-send-email-wenyou.yang@atmel.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v3 2/5] gpio: atmel_pio4: Rework to support DM & DT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Rework the driver to support driver model and device tree, and support to regard the pio4 pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang --- Changes in v3: - Add bind callback to support the pinctl device regarding as a child of atmel_pio4 device. - Add clock support. Changes in v2: None drivers/gpio/Kconfig | 2 +- drivers/gpio/atmel_pio4.c | 141 +++++++++++++++++++++++++++++++++++++++------- 2 files changed, 122 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 93a7e8c..11f056d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -30,7 +30,7 @@ config DWAPB_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" - depends on DM + depends on DM_GPIO default n help Say yes here to support the Atmel PIO4 driver. diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index 84e8cc5..6e7d095 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -7,11 +7,17 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include +#include +#include #include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; + static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) { struct atmel_pio4_port *base = NULL; @@ -165,14 +171,38 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) } #ifdef CONFIG_DM_GPIO + +struct atmel_pioctrl_data { + u32 nbanks; +}; + +struct atmel_pio4_platdata { + struct atmel_pio4_port *reg_base; +}; + +static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, + u32 bank) +{ + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = + (struct atmel_pio4_port *)((u32)plat->reg_base + + ATMEL_PIO_BANK_OFFSET * bank); + + return port_base; +} + static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); + u32 reg; writel(mask, &port_base->mskr); + reg = readl(&port_base->cfgr); + reg &= ~ATMEL_PIO_CFGR_FUNC_MASK; + reg &= ~ATMEL_PIO_DIR_MASK; writel(reg, &port_base->cfgr); return 0; @@ -181,12 +211,16 @@ static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) static int atmel_pio4_direction_output(struct udevice *dev, unsigned offset, int value) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); + u32 reg; writel(mask, &port_base->mskr); + reg = readl(&port_base->cfgr); + reg &= ~ATMEL_PIO_CFGR_FUNC_MASK; + reg |= ATMEL_PIO_DIR_MASK; writel(reg, &port_base->cfgr); if (value) @@ -199,9 +233,10 @@ static int atmel_pio4_direction_output(struct udevice *dev, static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); return (readl(&port_base->pdsr) & mask) ? 1 : 0; } @@ -209,9 +244,10 @@ static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) static int atmel_pio4_set_value(struct udevice *dev, unsigned offset, int value) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); if (value) writel(mask, &port_base->sodr); @@ -223,9 +259,10 @@ static int atmel_pio4_set_value(struct udevice *dev, static int atmel_pio4_get_function(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); writel(mask, &port_base->mskr); @@ -241,21 +278,85 @@ static const struct dm_gpio_ops atmel_pio4_ops = { .get_function = atmel_pio4_get_function, }; +static int atmel_pio4_bind(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + static int atmel_pio4_probe(struct udevice *dev) { - struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct atmel_pioctrl_data *pioctrl_data; + struct udevice *clkdev; + fdt_addr_t addr_base; + u32 nbanks; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clkdev); + if (ret) { + dev_err(dev, "Failed to find peripheral clock node\n"); + return -EINVAL; + } + + periph = fdtdec_get_uint(gd->fdt_blob, clkdev->of_offset, "reg", -1); + if (periph < 0) { + dev_err(dev, "Failed to find peripheral id\n"); + return -EINVAL; + } - uc_priv->bank_name = plat->bank_name; - uc_priv->gpio_count = ATMEL_PIO_NPINS_PER_BANK; + clkdev = dev_get_parent(clkdev); + if (!clkdev) { + dev_err(dev, "Failed to find parent node\n"); + return -ENODEV; + } + + ret = clk_enable(clkdev, periph); + if (ret) { + dev_err(dev, "Failed to enable peripheral clock\n"); + return ret; + } + + addr_base = dev_get_addr(dev); + if (addr_base == FDT_ADDR_T_NONE) + return -ENODEV; + + plat->reg_base = (struct atmel_pio4_port *)addr_base; + + pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev); + nbanks = pioctrl_data->nbanks; + + uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL); + uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK; return 0; } +/* + * The number of banks can be different from a SoC to another one. + * We can have up to 16 banks. + */ +static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { + .nbanks = 4, +}; + +static const struct udevice_id atmel_pio4_ids[] = { + { + .compatible = "atmel,sama5d2-gpio", + .data = (ulong)&atmel_sama5d2_pioctrl_data, + }, + {} +}; + U_BOOT_DRIVER(gpio_atmel_pio4) = { .name = "gpio_atmel_pio4", .id = UCLASS_GPIO, .ops = &atmel_pio4_ops, .probe = atmel_pio4_probe, + .bind = atmel_pio4_bind, + .of_match = atmel_pio4_ids, + .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata), }; + #endif