From patchwork Fri May 13 06:29:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miao Yan X-Patchwork-Id: 621854 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3r5g3M4wv1z9t44 for ; Fri, 13 May 2016 16:30:55 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Rr/flWuG; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB560A765B; Fri, 13 May 2016 08:30:35 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Vh21xM7eEMRM; Fri, 13 May 2016 08:30:35 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B97FCA7647; Fri, 13 May 2016 08:30:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB417A7532 for ; Fri, 13 May 2016 08:29:59 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ExnlnB0pgvuU for ; Fri, 13 May 2016 08:29:59 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f66.google.com (mail-pa0-f66.google.com [209.85.220.66]) by theia.denx.de (Postfix) with ESMTPS id 75070A750A for ; Fri, 13 May 2016 08:29:57 +0200 (CEST) Received: by mail-pa0-f66.google.com with SMTP id gh9so7857949pac.0 for ; Thu, 12 May 2016 23:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=PdcLbVxd/oo7USv3YLWtn0OGlvCyvOpd+cslnU7k9lk=; b=Rr/flWuGh1/xBxHDtqA7MNbb3oDlkJqJX3yedGUw0sgMxe4yotlVonHyC/hgVjb30U hCS6l6xsqR9mQzgemV88Lrd6VSyMBT7SG/QPu15dyyDDzceKtr+y5C1gywwt7W9bF/gG /NGJlxyevvqGI0vilnCfUcwhTLyLtQhUW+aZugOahB0FI7tfC5slNNH1cP0iuRfVQfD5 YdC8cyN9kQ4tFvogvUTlZwg7K63C3bOEY3EwzTuxcQYyWRkNRVDBTv4HT/M+BhDKvecf +0EkOUla8MPIuZUSUIFUIjKs0H0pakveGKSUOYL7w/T+zIA/tvZI4v9/pxDxarP8qsYM frRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=PdcLbVxd/oo7USv3YLWtn0OGlvCyvOpd+cslnU7k9lk=; b=YuKiLQ9kY8iNFo78841nuNtirU2osOdDcjrv9z1eHualBzrP2ZZNozQDuvo6zLyMBd cGjUeaeWBc3pu4AtPQ+pSUUlBGKe3zJB3VVmEwZ54dMvlPhnhtqC7yGd/sFvOcNOYROe lbYq3gu1QB+g92jvFffMxEPjqQz+V2dWCkLlU+t1FY/SUtzIfs5yWpoHhqHnipyjGlwz m2A3+a3v66dbqEcjc0BHlJ0CnJhYKaeurcA2VL2wSWrz/kxUJtT6rukNOwANjJd5c1s2 Xbzu2/awS1QgGv+HlwhRj+m4HpV/CcNJaSwtLrNAauQYJwUn/6JHvhCe0Iu7qRbN+/5f ujMA== X-Gm-Message-State: AOPr4FWueuEdxzfGH1Ic5HaOaqbZv54Hoxd+OBtrfoGKwfj9ZIrRPSgXtMoUHcY0eCPS6w== X-Received: by 10.66.124.226 with SMTP id ml2mr20047722pab.90.1463120996579; Thu, 12 May 2016 23:29:56 -0700 (PDT) Received: from pa-dbc1131.eng.vmware.com ([208.91.1.34]) by smtp.gmail.com with ESMTPSA id t8sm24350787paw.16.2016.05.12.23.29.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 May 2016 23:29:56 -0700 (PDT) From: Miao Yan To: u-boot@lists.denx.de, trini@konsulko.com, sjg@chromium.org, bmeng.cn@gmail.com Date: Thu, 12 May 2016 23:29:38 -0700 Message-Id: <1463120984-19813-7-git-send-email-yanmiaobest@gmail.com> X-Mailer: git-send-email 2.6.3.444.gfd13a2e In-Reply-To: <1463120984-19813-1-git-send-email-yanmiaobest@gmail.com> References: <1463120984-19813-1-git-send-email-yanmiaobest@gmail.com> Subject: [U-Boot] [PATCH 06/12] x86: qemu: move x86 specific operations out of qfw core X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan Reviewed-by: Bin Meng --- arch/x86/cpu/qemu/qemu.c | 39 ++++++++++++++++++++++++++++++++++++++- drivers/misc/qemu_fw_cfg.c | 30 +++++++++++++----------------- include/qemu_fw_cfg.h | 15 +++++++++------ 3 files changed, 60 insertions(+), 24 deletions(-) diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 2631e99..d964283 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -17,6 +17,43 @@ static bool i440fx; +#ifdef CONFIG_QFW + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma) +{ + outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static struct fw_cfg_arch_ops fwcfg_x86_ops = { + .arch_read_pio = qemu_x86_fwcfg_read_entry_pio, + .arch_read_dma = qemu_x86_fwcfg_read_entry_dma +}; +#endif + static void enable_pm_piix(void) { u8 en; @@ -91,7 +128,7 @@ static void qemu_chipset_init(void) } #ifdef CONFIG_QFW - qemu_fwcfg_init(); + qemu_fwcfg_init(&fwcfg_x86_ops); #endif } diff --git a/drivers/misc/qemu_fw_cfg.c b/drivers/misc/qemu_fw_cfg.c index e726059..0700641 100644 --- a/drivers/misc/qemu_fw_cfg.c +++ b/drivers/misc/qemu_fw_cfg.c @@ -14,6 +14,7 @@ static bool fwcfg_present; static bool fwcfg_dma_present; +static struct fw_cfg_arch_ops *fwcfg_arch_ops; static LIST_HEAD(fw_list); @@ -21,17 +22,10 @@ static LIST_HEAD(fw_list); static void qemu_fwcfg_read_entry_pio(uint16_t entry, uint32_t size, void *address) { - uint32_t i = 0; - uint8_t *data = address; + debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n", + entry, size, address); - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - outw(entry, FW_CONTROL_PORT); - while (size--) - data[i++] = inb(FW_DATA_PORT); + return fwcfg_arch_ops->arch_read_pio(entry, size, address); } /* Read configuration item using fw_cfg DMA interface */ @@ -53,13 +47,10 @@ static void qemu_fwcfg_read_entry_dma(uint16_t entry, barrier(); - debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", - address, size, be32_to_cpu(dma.control)); - - outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); + debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n", + entry, size, address, be32_to_cpu(dma.control)); - while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) - __asm__ __volatile__ ("pause"); + fwcfg_arch_ops->arch_read_dma(&dma); } bool qemu_fwcfg_present(void) @@ -164,13 +155,18 @@ bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter) return iter->entry == &fw_list; } -void qemu_fwcfg_init(void) +void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops) { uint32_t qemu; uint32_t dma_enabled; fwcfg_present = false; fwcfg_dma_present = false; + fwcfg_arch_ops = NULL; + + if (!ops || !ops->arch_read_pio || !ops->arch_read_dma) + return; + fwcfg_arch_ops = ops; qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE) diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h index f718e09..b0b3b59 100644 --- a/include/qemu_fw_cfg.h +++ b/include/qemu_fw_cfg.h @@ -7,11 +7,6 @@ #ifndef __FW_CFG__ #define __FW_CFG__ -#define FW_CONTROL_PORT 0x510 -#define FW_DATA_PORT 0x511 -#define FW_DMA_PORT_LOW 0x514 -#define FW_DMA_PORT_HIGH 0x518 - #include enum qemu_fwcfg_items { @@ -97,6 +92,12 @@ struct fw_cfg_dma_access { __be64 address; }; +struct fw_cfg_arch_ops { + void (*arch_read_pio)(uint16_t selector, uint32_t size, + void *address); + void (*arch_read_dma)(struct fw_cfg_dma_access *dma); +}; + struct bios_linker_entry { __le32 command; union { @@ -148,8 +149,10 @@ struct bios_linker_entry { /** * Initialize QEMU fw_cfg interface + * + * @ops: arch specific read operations */ -void qemu_fwcfg_init(void); +void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops); void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address); int qemu_fwcfg_read_firmware_list(void);