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[147.11.157.139]) by smtp.gmail.com with ESMTPSA id lz5sm39128948pab.34.2016.05.09.02.31.04 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 May 2016 02:31:04 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Mon, 9 May 2016 02:34:28 -0700 Message-Id: <1462786477-14036-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1462786477-14036-1-git-send-email-bmeng.cn@gmail.com> References: <1462786477-14036-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 05/14] x86: Prepare configuration tables in dedicated high memory region X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc. Signed-off-by: Bin Meng --- arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/include/asm/coreboot_tables.h | 19 +++++++++++++++++++ arch/x86/include/asm/global_data.h | 4 ++++ arch/x86/lib/coreboot_table.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4ef27dc..d304e29 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -536,6 +536,20 @@ config SEABIOS Check http://www.seabios.org/SeaBIOS for details. +config HIGH_TABLE_SIZE + hex "Size of configuration tables which reside in high memory" + default 0x10000 + depends on SEABIOS + help + SeaBIOS itself resides in E seg and F seg, where U-Boot puts all + configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot + puts a copy of configuration tables in high memory region which + is reserved on the stack before relocation. The region size is + determined by this option. + + Increse it if the default size does not fit the board's needs. + This is most likely due to a large ACPI DSDT table is used. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 15ccf9b..e036f74 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -295,6 +295,25 @@ struct cbmem_entry { #define CBMEM_ID_NONE 0x00000000 /** + * high_table_reserve() - reserve configuration table in high memory + * + * This reserves configuration table in high memory. + * + * @return: always 0 + */ +int high_table_reserve(void); + +/** + * high_table_malloc() - allocate configuration table in high memory + * + * This allocates configuration table in high memory. + * + * @bytes: size of configuration table to be allocated + * @return: pointer to configuration table in high memory + */ +void *high_table_malloc(size_t bytes); + +/** * write_coreboot_table() - write coreboot table * * This writes coreboot table at a given address. diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3bc2ac2..7434f77 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,10 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ +#ifdef CONFIG_SEABIOS + u32 high_table_ptr; + u32 high_table_limit; +#endif }; #endif diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index cb45a79..ceab3cf 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -9,6 +9,37 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + +int high_table_reserve(void) +{ + /* adjust stack pointer to reserve space for configuration tables */ + gd->arch.high_table_limit = gd->start_addr_sp; + gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE; + gd->arch.high_table_ptr = gd->start_addr_sp; + + /* clear the memory */ + memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE); + + gd->start_addr_sp &= ~0xf; + + return 0; +} + +void *high_table_malloc(size_t bytes) +{ + u32 new_ptr; + void *ptr; + + new_ptr = gd->arch.high_table_ptr + bytes; + if (new_ptr >= gd->arch.high_table_limit) + return NULL; + ptr = (void *)gd->arch.high_table_ptr; + gd->arch.high_table_ptr = new_ptr; + + return ptr; +} + /** * cb_table_init() - initialize a coreboot table header *