From patchwork Mon May 2 11:36:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Scheel X-Patchwork-Id: 617480 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qz2Lx3wjQz9t3x for ; Mon, 2 May 2016 21:36:25 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AA9FBA7719; Mon, 2 May 2016 13:36:21 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AWRTUwLgkFvG; Mon, 2 May 2016 13:36:21 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CE47DA76E6; Mon, 2 May 2016 13:36:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8F2C5A74E3 for ; Mon, 2 May 2016 13:36:12 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ccUIpJwpug3V for ; Mon, 2 May 2016 13:36:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from web01.jusst.de (jusst.de [188.40.114.84]) by theia.denx.de (Postfix) with ESMTPS id 65885A74D0 for ; Mon, 2 May 2016 13:36:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by web01.jusst.de (Postfix) with ESMTP id 1D5A21B0107D; Mon, 2 May 2016 13:36:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at web01.jusst.de Received: from web01.jusst.de ([127.0.0.1]) by localhost (web01.jusst.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LRsyNt65zB7L; Mon, 2 May 2016 13:36:11 +0200 (CEST) Received: from avionic-0108.net.jusst.de. (p5B3C05C2.dip0.t-ipconnect.de [91.60.5.194]) (Authenticated sender: julian@jusst.de) by web01.jusst.de (Postfix) with ESMTPSA id 53C8A1B02D56; Mon, 2 May 2016 13:36:11 +0200 (CEST) From: Julian Scheel To: twarren@nvidia.com, swarren@wwwdotorg.org, u-boot@lists.denx.de, treding@nvidia.com Date: Mon, 2 May 2016 13:36:06 +0200 Message-Id: <1462188966-32476-2-git-send-email-julian@jusst.de> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1462188966-32476-1-git-send-email-julian@jusst.de> References: <1462188966-32476-1-git-send-email-julian@jusst.de> Subject: [U-Boot] [PATCH 2/2] tegra: Add watchdog driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for the tegra (t30 and newer) watchdog component. Signed-off-by: Julian Scheel --- arch/arm/include/asm/arch-tegra/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra/wdt.h | 41 ++++++++++++++++++++++ arch/arm/mach-tegra/board2.c | 4 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/tegra_wdt.c | 60 +++++++++++++++++++++++++++++++++ 5 files changed, 108 insertions(+) create mode 100644 arch/arm/include/asm/arch-tegra/wdt.h create mode 100644 drivers/watchdog/tegra_wdt.c diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3..790a7ae 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -11,6 +11,8 @@ #define NV_PA_ARM_PERIPHBASE 0x50040000 #define NV_PA_PG_UP_BASE 0x60000000 #define NV_PA_TMRUS_BASE 0x60005010 +#define NV_PA_TMR5_BASE 0x60005060 +#define NV_PA_TMRWDT0_BASE 0x60005100 #define NV_PA_CLK_RST_BASE 0x60006000 #define NV_PA_FLOW_BASE 0x60007000 #define NV_PA_GPIO_BASE 0x6000D000 diff --git a/arch/arm/include/asm/arch-tegra/wdt.h b/arch/arm/include/asm/arch-tegra/wdt.h new file mode 100644 index 0000000..642b0b2 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/wdt.h @@ -0,0 +1,41 @@ +/* + * Copyright 2016 Avionic Design GmbH + * Copyright 2016 Julian Scheel + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_WDT_H_ +#define _TEGRA_WDT_H_ + +struct wdt_ctrl { + u32 config; + u32 status; + u32 command; + u32 unlock; +}; + +#define WDT_CFG_SOURCE_MASK 0xf + +#define WDT_CFG_PERIOD_SHIFT 4 +#define WDT_CFG_PERIOD_MASK (0xff << WDT_CFG_PERIOD_SHIFT) + +#define WDT_CFG_PMC2CAR_RST_EN (1 << 15) + +#define WDT_STS_COUNT_SHIFT 4 +#define WDT_STS_COUNT_MASK (0xff << WDT_STS_COUNT_SHIFT) + +#define WDT_CMD_START_COUNTER (1 << 0) +#define WDT_CMD_DISABLE_COUNTER (1 << 1) + +#define WDT_UNLOCK_PATTERN 0xc45a + +/* Timer registers */ +struct timer_ctrl { + u32 ptv; +}; + +#define TIMER_PTV_EN (1 << 31) +#define TIMER_PTV_PERIODIC (1 << 30) + +#endif /* _TEGRA_WDT_H_ */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 896c1cc..77426f3 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -124,6 +124,10 @@ int board_init(void) tegra_gpu_config(); +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + #ifdef CONFIG_TEGRA_SPI pin_mux_spi(); #endif diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a007ae8..e580e1b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o diff --git a/drivers/watchdog/tegra_wdt.c b/drivers/watchdog/tegra_wdt.c new file mode 100644 index 0000000..70c0de7 --- /dev/null +++ b/drivers/watchdog/tegra_wdt.c @@ -0,0 +1,60 @@ +/* + * Copyright 2016 Avionic Design GmbH + * Copyright 2016 Julian Scheel + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* Timeout in seconds */ +#define WDT_TIMEOUT 60 + +/* Timer to use - 5 is used in linux kernel */ +#define WDT_TIMER_ID 5 +void hw_watchdog_init(void) +{ + struct timer_ctrl *timer = (struct timer_ctrl *)NV_PA_TMR5_BASE; + struct wdt_ctrl *wdt = (struct wdt_ctrl *)NV_PA_TMRWDT0_BASE; + u32 val; + + /* Timer runs fixed at 1 MHz, reset is triggered at 4th timeout of + * timer */ + val = 1000000ul / 4; + val |= (TIMER_PTV_EN | TIMER_PTV_PERIODIC); + writel(val, &timer->ptv); + + /* Setup actual wdt */ + val = WDT_TIMER_ID | + ((WDT_TIMEOUT << WDT_CFG_PERIOD_SHIFT) & WDT_CFG_PERIOD_MASK) | + WDT_CFG_PMC2CAR_RST_EN; + writel(val, &wdt->config); + + /* Activate the wdt */ + writel(WDT_CMD_START_COUNTER, &wdt->command); +} + +void hw_watchdog_reset(void) +{ + struct wdt_ctrl *wdt = (struct wdt_ctrl *)NV_PA_TMRWDT0_BASE; + + /* Activate the wdt */ + writel(WDT_CMD_START_COUNTER, &wdt->command); +} + +void hw_watchdog_disable(void) +{ + struct timer_ctrl *timer = (struct timer_ctrl *)NV_PA_TMR5_BASE; + struct wdt_ctrl *wdt = (struct wdt_ctrl *)NV_PA_TMRWDT0_BASE; + + /* Write unlock pattern */ + writel(WDT_UNLOCK_PATTERN, &wdt->unlock); + /* Disable wdt */ + writel(WDT_CMD_DISABLE_COUNTER, &wdt->command); + /* Stop timer */ + writel(0, &timer->ptv); +}