From patchwork Tue Apr 19 20:59:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 612356 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qqHjx064fz9t6J for ; Wed, 20 Apr 2016 07:11:01 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 632B1A78A2; Tue, 19 Apr 2016 23:05:28 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WX7y_in0_mvO; Tue, 19 Apr 2016 23:05:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37EF7A772F; Tue, 19 Apr 2016 23:02:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E6CDA778F for ; Tue, 19 Apr 2016 23:01:46 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZdYSVXZPpiA2 for ; Tue, 19 Apr 2016 23:01:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from avon.wwwdotorg.org (avon.wwwdotorg.org [70.85.31.133]) by theia.denx.de (Postfix) with ESMTPS id EA93CA76F2 for ; Tue, 19 Apr 2016 23:00:43 +0200 (CEST) Received: from swarren-lx1.nvidia.com (thunderhill.nvidia.com [216.228.112.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id CE1F61C0422; Tue, 19 Apr 2016 15:00:40 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99 at avon.wwwdotorg.org From: Stephen Warren To: u-boot@lists.denx.de, Simon Glass , Tom Warren , Stephen Warren Date: Tue, 19 Apr 2016 14:59:27 -0600 Message-Id: <1461099580-3866-48-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461099580-3866-1-git-send-email-swarren@wwwdotorg.org> References: <1461099580-3866-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public Subject: [U-Boot] [PATCH 47/60] ARM: tegra: provide API for SPL code to init UART X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stephen Warren Currently, SPL console initialization on Tegra suffers from two problems: 1) It's a monolithic function that knows about all possibilities using tables and ifdefs set by board config.h, and contained in core files that are always built into U-Boot. Some of the code can't be ported to future SoCs since the clock APIs will be different. Equally, future SoCs don't need the code since earlier boot FW will always initialized the UART. 2) It's unnecessarily invoked twice, once by SPL and once by the main U-Boot binary. This patch adds simpler APIs to initialize the UART from SPL. This code can be omitted from non-SPL builds. A future patch will add the code to the Makefile when board files are converted. Adding it now would cause duplicate symbols for the UART device itself which will cause the link to fail. Even if that were resolved by changing the symbol name, duplicate UART devices would be registered, which would likely cause runtime problems. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass --- arch/arm/mach-tegra/include/mach/spl_uart.h | 20 +++++++++++++++ arch/arm/mach-tegra/spl_uart.c | 39 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-tegra/include/mach/spl_uart.h create mode 100644 arch/arm/mach-tegra/spl_uart.c diff --git a/arch/arm/mach-tegra/include/mach/spl_uart.h b/arch/arm/mach-tegra/include/mach/spl_uart.h new file mode 100644 index 000000000000..28b14acce93b --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/spl_uart.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MACH_SPL_UART_H +#define _MACH_SPL_UART_H + +enum tegra_spl_uart { + TEGRA_SPL_UART_A, + TEGRA_SPL_UART_B, + TEGRA_SPL_UART_C, + TEGRA_SPL_UART_D, + TEGRA_SPL_UART_E, +}; + +void tegra_spl_setup_uart(enum tegra_spl_uart uart_id); + +#endif diff --git a/arch/arm/mach-tegra/spl_uart.c b/arch/arm/mach-tegra/spl_uart.c new file mode 100644 index 000000000000..2c1d237174fd --- /dev/null +++ b/arch/arm/mach-tegra/spl_uart.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +static struct ns16550_platdata ns16550_com1_pdata = { + .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_com1) = { + "ns16550_serial", &ns16550_com1_pdata +}; + +static const struct { + unsigned long addr; + enum periph_id periph_id; +} uart_info[] = { + { NV_PA_APB_UARTA_BASE, PERIPH_ID_UART1, }, + { NV_PA_APB_UARTB_BASE, PERIPH_ID_UART2, }, + { NV_PA_APB_UARTC_BASE, PERIPH_ID_UART3, }, + { NV_PA_APB_UARTD_BASE, PERIPH_ID_UART4, }, + { NV_PA_APB_UARTE_BASE, PERIPH_ID_UART5, }, +}; + +void tegra_spl_setup_uart(unsigned int uart_id) +{ + if (uart_id >= ARRAY_SIZE(uart_info)) + return; + clock_ll_start_uart(uart_info[uart_id].periph_id); + ns16550_com1_pdata.base = uart_info[uart_id].addr; +}