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BN3PR0301MB1217; 5:8lR/ZUz4lLscNw4kBnNLoBYRZjy3GAToyDoYjrBTZVO5ZeXEqxB66UngLvnMG9WNRzIavQzL9q/PXRfvefMZxH9h/EF80QTYvsHtlQ5yM2BUImrU+j3ee6i8F0RbjzjBzlBVXNaPqLOFWjrPHRhzmKCwUSt8126cOZZonCE8bE8=; 24:QUQJbLn3UEfaoKvPIL+yYSGsO/e5H0/2G3ILgf3/6LYUImUgKTTDAaJKML7GZIz94kOCtwCdOqMcGcq/wkUwT55w4OsErM+kw+1u1VSIWWA= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2016 08:31:33.8717 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0301MB1217 Subject: [U-Boot] [PATCH v2] armv8/ls1043: Add workaround for DDR erratum A-008850 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu --- v2: moved part 2 of 2 to public soc.c arch/arm/cpu/armv8/fsl-layerscape/soc.c | 36 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + board/freescale/ls1043aqds/ddr.c | 1 + board/freescale/ls1043aqds/ddr.h | 2 ++ board/freescale/ls1043aqds/ls1043aqds.c | 8 ----- board/freescale/ls1043ardb/ddr.c | 2 ++ board/freescale/ls1043ardb/ddr.h | 3 ++ board/freescale/ls1043ardb/ls1043ardb.c | 8 ----- include/fsl_ddr_sdram.h | 4 +++ 9 files changed, 49 insertions(+), 16 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0cb0100..0fb5c7f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #ifdef CONFIG_CHAIN_OF_TRUST #include #endif @@ -271,6 +273,39 @@ static void erratum_a009660(void) #endif } +static void erratum_a008850_early(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + +void erratum_a008850_post(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -295,6 +330,7 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* Erratum */ + erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..a24dc28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -191,6 +191,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 3d3c533..0fd835d 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -116,6 +116,7 @@ phys_size_t initdram(int board_type) dram_size = fsl_ddr_sdram(); #endif + erratum_a008850_post(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h index 8adb660..d3f4082 100644 --- a/board/freescale/ls1043aqds/ddr.h +++ b/board/freescale/ls1043aqds/ddr.h @@ -7,6 +7,8 @@ #ifndef __DDR_H__ #define __DDR_H__ +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index fba6b88..fc097d9 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -307,14 +307,6 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *) - CONFIG_SYS_CCI400_ADDR; - - /* Set CCI-400 control override register to enable barrier - * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 11bc0f2..1e2fd2e 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -177,6 +177,8 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + erratum_a008850_post(); + #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index b17eb80..8ca166b 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -6,6 +6,9 @@ #ifndef __DDR_H__ #define __DDR_H__ + +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index ec5fdbf..8d80135 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -83,14 +83,6 @@ int board_early_init_f(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4..44ae7fb 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000