From patchwork Wed Mar 30 17:58:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 603556 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qZwPD3p2Gz9sD1 for ; Thu, 31 Mar 2016 04:58:40 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5F405A750A; Wed, 30 Mar 2016 19:58:37 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qkax08lzJKzu; Wed, 30 Mar 2016 19:58:37 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D0B73A749F; Wed, 30 Mar 2016 19:58:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E1228A749F for ; Wed, 30 Mar 2016 19:58:33 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zzxLPQB0dt8p for ; Wed, 30 Mar 2016 19:58:33 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 5E596A7498 for ; Wed, 30 Mar 2016 19:58:28 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2UHwQvk007349; Wed, 30 Mar 2016 12:58:26 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2UHwQx6024390; Wed, 30 Mar 2016 12:58:26 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Wed, 30 Mar 2016 12:58:26 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2UHwQOJ011034; Wed, 30 Mar 2016 12:58:26 -0500 Received: from localhost (a0272616local.am.dhcp.ti.com [128.247.83.223]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u2UHwQ905835; Wed, 30 Mar 2016 12:58:26 -0500 (CDT) From: Dan Murphy To: Date: Wed, 30 Mar 2016 12:58:37 -0500 Message-ID: <1459360717-10395-1-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 2.7.2.333.g70bd996 MIME-Version: 1.0 Cc: trini@konsulko.com Subject: [U-Boot] [PATCH] board: ti: DRA7: Add DP83867 TI phy for rev c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable the TI DP83867 Giga bit phy on the dra7 rev c board. The rx and tx internal delays are need for this board so the usage of RGMII_ID is required. Signed-off-by: Dan Murphy Acked-by: Mugunthan V N Reviewed-by: Tom Rini --- board/ti/dra7xx/evm.c | 6 ++++++ include/configs/dra7xx_evm.h | 1 + 2 files changed, 7 insertions(+) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 25f2031..9bd71d8 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "mux_data.h" #include "../common/board_detect.h" @@ -679,6 +680,11 @@ int board_eth_init(bd_t *bis) if (*omap_si_rev == DRA722_ES1_0) cpsw_data.active_slave = 1; + if (board_is_dra72x_revc_or_later()) { + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; + } + ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index c0795ab..7734e8d 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -155,6 +155,7 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB +#define CONFIG_PHY_TI /* SPI */ #undef CONFIG_OMAP3_SPI