From patchwork Mon Mar 21 13:50:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 600131 X-Patchwork-Delegate: hdegoede@redhat.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qTHK460rBz9s4x for ; Tue, 22 Mar 2016 00:50:32 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3E7AEA7517; Mon, 21 Mar 2016 14:50:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WO10heaoZzCj; Mon, 21 Mar 2016 14:50:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87797A74D0; Mon, 21 Mar 2016 14:50:30 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D54FA74D0 for ; Mon, 21 Mar 2016 14:50:27 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Tx3j395PTw6q for ; Mon, 21 Mar 2016 14:50:27 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by theia.denx.de (Postfix) with ESMTPS id 12069A748F for ; Mon, 21 Mar 2016 14:50:24 +0100 (CET) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id 78BF48A14E; Mon, 21 Mar 2016 13:50:22 +0000 (UTC) Received: from shalem.localdomain.com (vpn1-7-224.ams2.redhat.com [10.36.7.224]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u2LDoJZ7001721; Mon, 21 Mar 2016 09:50:20 -0400 From: Hans de Goede To: Ian Campbell Date: Mon, 21 Mar 2016 14:50:16 +0100 Message-Id: <1458568216-18179-1-git-send-email-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer working X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The 2nd usb controller on sun4i/sun7i has its base address 0x8000 bytes from the 1st one, rather then 0x1000. Also the ahb clk gates are interleaved with the ohci clk-gates introducing a hole between the clks for usb1 and usb2. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/usb/host/ehci-sunxi.c | 13 +++++++++++-- drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++--- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index cf3dcc4..677a5d3 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -17,6 +17,14 @@ #include #include "ehci.h" +#ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 +#define AHB_CLK_DIST 2 +#else +#define BASE_DIST 0x1000 +#define AHB_CLK_DIST 1 +#endif + struct ehci_sunxi_priv { struct ehci_ctrl ehci; int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ @@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev) #ifdef CONFIG_MACH_SUN8I_H3 priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif - priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1; - priv->ahb_gate_mask <<= priv->phy_index - 1; + priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST; + priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; + priv->phy_index++; /* Non otg phys start at 1 */ setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); #ifdef CONFIG_SUNXI_GEN_SUN6I diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 1b1f651..d4fb95a 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -17,6 +17,14 @@ #include #include "ohci.h" +#ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 +#define AHB_CLK_DIST 2 +#else +#define BASE_DIST 0x1000 +#define AHB_CLK_DIST 1 +#endif + struct ohci_sunxi_priv { ohci_t ohci; int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ @@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev) priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0; #endif priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1; - priv->ahb_gate_mask <<= priv->phy_index - 1; - priv->usb_gate_mask <<= priv->phy_index - 1; + priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; + priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; + priv->usb_gate_mask <<= priv->phy_index; + priv->phy_index++; /* Non otg phys start at 1 */ setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);