| Message ID | 1458107423-9841-3-git-send-email-Shengzhou.Liu@nxp.com |
|---|---|
| State | Accepted |
| Commit | 5fc62fe57097e195a8047859cd3c278a5d6790b6 |
| Delegated to: | York Sun |
| Headers | show |
On 03/15/2016 10:59 PM, Shengzhou Liu wrote: > The initial training for the DDRC may provide results that are not > optimized. The workaround provides better read timing margins. > > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> > --- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + > drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++++ > include/fsl_ddr_sdram.h | 4 ++++ > 3 files changed, 12 insertions(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index 6ec7e50..ba06465 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -119,6 +119,7 @@ > #define CONFIG_SYS_FSL_ERRATUM_A008751 > #define CONFIG_SYS_FSL_ERRATUM_A009635 > #define CONFIG_SYS_FSL_ERRATUM_A009663 > +#define CONFIG_SYS_FSL_ERRATUM_A009801 > #define CONFIG_SYS_FSL_ERRATUM_A009803 > #define CONFIG_SYS_FSL_ERRATUM_A009942 > > diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c > index 7cdb700..1dc0631 100644 > --- a/drivers/ddr/fsl/fsl_ddr_gen4.c > +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c > @@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, > } > #endif > > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801 > + temp32 = ddr_in32(&ddr->debug[25]); > + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; > + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; > + ddr_out32(&ddr->debug[25], temp32); > +#endif > + Shengzhou, Please examine workaround for A008511. This workaround has been included, but wasn't named as A009801. You can move out that code and put under A009801 if like. York
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6ec7e50..ba06465 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -119,6 +119,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A009801 #define CONFIG_SYS_FSL_ERRATUM_A009803 #define CONFIG_SYS_FSL_ERRATUM_A009942 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 7cdb700..1dc0631 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801 + temp32 = ddr_in32(&ddr->debug[25]); + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; + ddr_out32(&ddr->debug[25], temp32); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; tmp = ddr_in32(&ddr->debug[28]); diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index acddf14..486e47e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_26 register */ +#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ +#define DDR_CAS_TO_PRE_SUB_SHIFT 12 + /* DEBUG_29 register */ #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++++ include/fsl_ddr_sdram.h | 4 ++++ 3 files changed, 12 insertions(+)