From patchwork Sat Mar 12 05:07:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 596617 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qMXPC1w0dz9s3s for ; Sat, 12 Mar 2016 16:19:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=SyoYVYOG; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3FDD1A76B2; Sat, 12 Mar 2016 06:17:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3ym0FL0qFYum; Sat, 12 Mar 2016 06:17:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6ABABA773C; Sat, 12 Mar 2016 06:17:10 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 08D7DA768D for ; Sat, 12 Mar 2016 06:16:00 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wJjgafKqKxvU for ; Sat, 12 Mar 2016 06:15:59 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ig0-f178.google.com (mail-ig0-f178.google.com [209.85.213.178]) by theia.denx.de (Postfix) with ESMTPS id 09A43A7535 for ; Sat, 12 Mar 2016 06:15:56 +0100 (CET) Received: by mail-ig0-f178.google.com with SMTP id av4so27559418igc.1 for ; Fri, 11 Mar 2016 21:15:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=m5RPBwR/QUAnG3AaI2paTYBPOBzWNhFjyhdsraf/JZw=; b=SyoYVYOG0Gs2+sLPw8n1TNluFKOqRT0ECi8M1vZHQQYXyu+ZQ2JTgFmFvpfIhFrJSB JIqOg1Ot+KbEFhM+TjimB/HV/D3tYwlkBTy1t7p56B0myCQOxCnM3oh6Ed5L6htgmxCJ KWLR3q+N83udEI/qLPARJWvYJUwKFxWBvAsFoMaaL0NS1Yu1lT81slVAFM/TfIhODsz5 z2Uac1ZhQib9L6SHLUVEH+hy1oeRPo4/YuTUpvfXFUz/WuBPhGlo95slWK6a0a9qlxE6 bO3QFRj+O0J9Q9snkNcxGnYuNejaKevl+zXdMIc8Mbs9DU1RD6oBmnKgYhmoSreukRCK /d/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=m5RPBwR/QUAnG3AaI2paTYBPOBzWNhFjyhdsraf/JZw=; b=mPWJsRvujsOsnn1nf8lFnSU5OkDur8H017FRdrg/UNflnm0POsR6PFCqop9nHyqXdn 8YYjzI6hoNVct1RnIOKAng+7YqPg7NOmyWNc8mezDCce6m3XPX3wlNWGpi1BT9nN/hTY v2NE5mN8lT+SquEkKdGkn7RpegIO94GCjSSCeHinjELc/6S6v6TtNwErvnhmzyKk3rco dEgzedRaKmyXmO2+wFZ9s7pGIdlAuCxGVhoZIYtIW35bosE51VClTAwVD6T5W2X5DPs8 1C6SioiMdDEZterWhQC9WR1GlrrSdYl2TE/YvaQ9ih/hFsg12cBIL7+EBcDWFUdaW6J5 jvew== X-Gm-Message-State: AD7BkJL3VwDVPNnCl0KAgjyHAmBY7JvMucYEnkL0l6kMroe4KpKlo74DbXEcrwS+vx8/WGqr X-Received: by 10.50.70.4 with SMTP id i4mr2401713igu.21.1457759755533; Fri, 11 Mar 2016 21:15:55 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id qs9sm252587igb.16.2016.03.11.21.15.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Mar 2016 21:15:53 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 8F6FD223220; Fri, 11 Mar 2016 22:07:50 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 11 Mar 2016 22:07:28 -0700 Message-Id: <1457759256-23432-44-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: <1457759256-23432-1-git-send-email-sjg@chromium.org> References: <1457759256-23432-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v2 43/51] x86: broadwell: Add support for high-speed I/O lane with ME X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass Acked-by: Bin Meng --- Changes in v2: None arch/x86/cpu/broadwell/Makefile | 1 + arch/x86/cpu/broadwell/me.c | 57 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/x86/cpu/broadwell/me.c diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index 012798f..7edb6f6 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -7,6 +7,7 @@ obj-y += cpu.o obj-y += iobp.o obj-y += lpc.o +obj-y += me.o obj-y += northbridge.o obj-y += pch.o obj-y += pinctrl_broadwell.o diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c new file mode 100644 index 0000000..e03b87c --- /dev/null +++ b/arch/x86/cpu/broadwell/me.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + * + * Based on code from coreboot src/soc/intel/broadwell/me_status.c + */ + +#include +#include +#include + +static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset) +{ + u32 dword; + + dm_pci_read_config32(dev, offset, &dword); + memcpy(ptr, &dword, sizeof(dword)); +} + +int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp, + uint16_t *checksump) +{ + int count; + u32 hsiover; + struct me_hfs hfs; + + /* Query for HSIO version, overloads H_GS and HFS */ + dm_pci_write_config32(dev, PCI_ME_H_GS, + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + me_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + debug("ERROR: ME failed to respond\n"); + return -ETIMEDOUT; + } + + /* HSIO version should be in HFS_5 */ + dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover); + *versionp = hsiover >> 16; + *checksump = hsiover & 0xffff; + + debug("ME: HSIO Version : %d (CRC 0x%04x)\n", + *versionp, *checksump); + + /* Reset registers to normal behavior */ + dm_pci_write_config32(dev, PCI_ME_H_GS, + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); + + return 0; +}