From patchwork Sat Mar 12 05:07:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 596607 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qMXLc5BmVz9sDG for ; Sat, 12 Mar 2016 16:16:56 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=Hl18ej4V; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10368A7728; Sat, 12 Mar 2016 06:16:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nLsPyeIevIBu; Sat, 12 Mar 2016 06:16:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 42060A7731; Sat, 12 Mar 2016 06:16:08 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D143A7687 for ; Sat, 12 Mar 2016 06:15:55 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UCDNFazyeOtT for ; Sat, 12 Mar 2016 06:15:55 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ig0-f170.google.com (mail-ig0-f170.google.com [209.85.213.170]) by theia.denx.de (Postfix) with ESMTPS id 0A88AA74BA for ; Sat, 12 Mar 2016 06:15:50 +0100 (CET) Received: by mail-ig0-f170.google.com with SMTP id ig19so27004425igb.1 for ; Fri, 11 Mar 2016 21:15:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=v2FRSQvJc7Q4kzJsgyYNH54wGNUiXTgXI6HZyoryqjM=; b=Hl18ej4V8VNwgxXifNcFRL7oCaDZYYY5KsZUPv2zgYZ/Ci4bswTcujZO7IAHjV8eHp RgR5/RmIzr6ckjpAfH9JMVrCuvOeMRZZCC09/6Orn8Nw5dmyakNiqRognFI1U+tqbsVx LJW/y/5pfU8cd6ZEEqmg2juPEbnVxaUjahtayJ/CJVHLyXWeSbbB+kwhoRf++iq6eCei I8C0a8Chf1owZrmhGG1BCHdu85vZfudLIOvKmnQqyVmy+tYXtdY9OQRkRDIIw3YJ54a8 6JfiAqSxm4/3TztSPxTiSVXGhAX/o8VAMul67wU2dJnEIVrnV3xCJEV22GjezjC3DARI a4jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=v2FRSQvJc7Q4kzJsgyYNH54wGNUiXTgXI6HZyoryqjM=; b=TRVmYO9qN0dK2MZoH7StZZ2tz9qYafjNiZX1H0ABvRmhCw7BXUJl64wEm+j5Z7Ga8c JhmFX7CZjYCJgfrjve+HXvXYXioWjkcGvi0Yy9xC8PwLeU/ltoKUv7bVxNkn17ZsVfPH v6tvogPRSBCyQyfv0UpiMPtZXG66VdnyUeOltbD663DDysrMnZQ0HiQZAsMWze09T3y4 ux82wBlX9Hon7vqmiaqXD0B8Pa3MLmOJPZyRagrP7h3S+agc3+hHfV8T8n3ROfv+nlM3 W1bekG8lMD88iK9vUFJOJ9+chSDgC9rwnKzKrVNkjkLVaAOY8XJbsjsK5KyzS15idpPs Vsng== X-Gm-Message-State: AD7BkJL+/qTNqd5Bhz3UyLbBcpRn2AcBH52a2XBUPnWladJuW7loKduWvOI20s04tFFg6ImG X-Received: by 10.50.78.130 with SMTP id b2mr7363094igx.71.1457759749387; Fri, 11 Mar 2016 21:15:49 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id g67sm4956124ioe.34.2016.03.11.21.15.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Mar 2016 21:15:46 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 70C432219B2; Fri, 11 Mar 2016 22:07:50 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 11 Mar 2016 22:07:27 -0700 Message-Id: <1457759256-23432-43-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: <1457759256-23432-1-git-send-email-sjg@chromium.org> References: <1457759256-23432-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v2 42/51] x86: broadwell: Add a GPIO driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a GPIO driver for the GPIO peripheral found on broadwell devices. Signed-off-by: Simon Glass Acked-by: Bin Meng --- Changes in v2: - Use setio_32() instead of setio_le32(), etc. - Fix 'configure' typo drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/intel_broadwell_gpio.c | 198 ++++++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+) create mode 100644 drivers/gpio/intel_broadwell_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 94fabb9..a5da5e7 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -39,6 +39,15 @@ config ATMEL_PIO4 may be dedicated as a general purpose I/O or be assigned to a function of an embedded peripheral. +config INTEL_BROADWELL_GPIO + bool "Intel Broadwell GPIO driver" + depends on DM + help + This driver supports Broadwell U devices which have an expanded + GPIO feature set. The difference is large enough to merit a separate + driver from the common Intel ICH6 driver. It supports a total of + 95 GPIOs which can be configured from the device tree. + config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ca8c487..e7b7ec4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_DM_GPIO) += gpio-uclass.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o +obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c new file mode 100644 index 0000000..8cf76f9 --- /dev/null +++ b/drivers/gpio/intel_broadwell_gpio.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct broadwell_bank_priv - Private driver data + * + * @regs: Pointer to GPIO registers + * @bank: Bank number for this bank (0, 1 or 2) + * @offset: GPIO offset for this bank (0, 32 or 64) + */ +struct broadwell_bank_priv { + struct pch_lp_gpio_regs *regs; + int bank; + int offset; +}; + +static int broadwell_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct pch_lp_gpio_regs *regs = priv->regs; + u32 val; + + /* + * Make sure that the GPIO pin we want isn't already in use for some + * built-in hardware function. We have to check this for every + * requested pin. + */ + debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset); + val = inl(®s->own[priv->bank]); + if (!(val & (1UL << offset))) { + debug("gpio is reserved for internal use\n"); + return -EPERM; + } + debug("ok\n"); + + return 0; +} + +static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct pch_lp_gpio_regs *regs = priv->regs; + + setio_32(®s->config[priv->offset + offset], CONFA_DIR_INPUT); + + return 0; +} + +static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct pch_lp_gpio_regs *regs = priv->regs; + + return inl(®s->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ? + 1 : 0; +} + +static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct pch_lp_gpio_regs *regs = priv->regs; + + debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset, + value); + clrsetio_32(®s->config[priv->offset + offset], CONFA_OUTPUT_HIGH, + value ? CONFA_OUTPUT_HIGH : 0); + + return 0; +} + +static int broadwell_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct pch_lp_gpio_regs *regs = priv->regs; + + broadwell_gpio_set_value(dev, offset, value); + clrio_32(®s->config[priv->offset + offset], CONFA_DIR_INPUT); + + return 0; +} + +static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct pch_lp_gpio_regs *regs = priv->regs; + u32 mask = 1UL << offset; + + if (!(inl(®s->own[priv->bank]) & mask)) + return GPIOF_FUNC; + if (inl(®s->config[priv->offset + offset]) & CONFA_DIR_INPUT) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static int broadwell_gpio_probe(struct udevice *dev) +{ + struct broadwell_bank_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct udevice *pinctrl; + int ret; + + /* Set up pin control if available */ + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); + debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret); + + uc_priv->gpio_count = GPIO_PER_BANK; + uc_priv->bank_name = plat->bank_name; + + priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr; + priv->bank = plat->bank; + priv->offset = priv->bank * 32; + debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs, + priv->bank); + + return 0; +} + +static int broadwell_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct broadwell_bank_platdata *plat = dev_get_platdata(dev); + u32 gpiobase; + int bank; + int ret; + + ret = pch_get_gpio_base(dev->parent, &gpiobase); + if (ret) + return ret; + + bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); + if (bank == -1) { + debug("%s: Invalid bank number %d\n", __func__, bank); + return -EINVAL; + } + plat->bank = bank; + plat->base_addr = gpiobase; + plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "bank-name", NULL); + + return 0; +} + +static int broadwell_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static const struct dm_gpio_ops gpio_broadwell_ops = { + .request = broadwell_gpio_request, + .direction_input = broadwell_gpio_direction_input, + .direction_output = broadwell_gpio_direction_output, + .get_value = broadwell_gpio_get_value, + .set_value = broadwell_gpio_set_value, + .get_function = broadwell_gpio_get_function, + .xlate = broadwell_gpio_xlate, +}; + +static const struct udevice_id intel_broadwell_gpio_ids[] = { + { .compatible = "intel,broadwell-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_broadwell) = { + .name = "gpio_broadwell", + .id = UCLASS_GPIO, + .of_match = intel_broadwell_gpio_ids, + .ops = &gpio_broadwell_ops, + .ofdata_to_platdata = broadwell_gpio_ofdata_to_platdata, + .probe = broadwell_gpio_probe, + .priv_auto_alloc_size = sizeof(struct broadwell_bank_priv), + .platdata_auto_alloc_size = sizeof(struct broadwell_bank_platdata), +};