From patchwork Wed Mar 9 12:09:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 595031 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B9AEC1402A1 for ; Wed, 9 Mar 2016 23:13:47 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E991A7706; Wed, 9 Mar 2016 13:13:45 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0nt5gqDRba-E; Wed, 9 Mar 2016 13:13:45 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B24084BF63; Wed, 9 Mar 2016 13:13:44 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 85D2B4BF63 for ; Wed, 9 Mar 2016 13:13:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L6FiN17vUqns for ; Wed, 9 Mar 2016 13:13:42 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 18F004BED0 for ; Wed, 9 Mar 2016 13:13:38 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u29CDaSa008653; Wed, 9 Mar 2016 06:13:36 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u29CDaA1029333; Wed, 9 Mar 2016 06:13:36 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Wed, 9 Mar 2016 06:13:35 -0600 Received: from a0131933.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u29CDXwV011075; Wed, 9 Mar 2016 06:13:34 -0600 From: Lokesh Vutla To: , Date: Wed, 9 Mar 2016 17:39:56 +0530 Message-ID: <1457525396-27240-1-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Cc: Tero Kristo , Sekhar Nori Subject: [U-Boot] [PATCH] ARM: DRA7: DDR: Enable SR in Power Management Control X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nishanth Menon If EMIF is idle for certain amount of DDR cycles, EMIF will put the DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register is programmed. And also before entering suspend-resume ddr needs to be put in self-refresh. Linux kernel does not program this register before entering suspend and relies on u-boot setting. So configuring it in u-boot. Signed-off-by: Nishanth Menon Signed-off-by: Lokesh Vutla Tested-by: Tom Rini Reviewed-by: Tom Rini --- arch/arm/include/asm/emif.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 3183130..b00dece 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -914,8 +914,8 @@ struct dmm_lisa_map_regs { /* Maximum delay before Low Power Modes */ #define REG_CS_TIM 0x0 -#define REG_SR_TIM 0x0 -#define REG_PD_TIM 0x0 +#define REG_SR_TIM 0xF +#define REG_PD_TIM 0xF /* EMIF_PWR_MGMT_CTRL register */ @@ -923,7 +923,7 @@ struct dmm_lisa_map_regs { ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ - ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\ + ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\ & EMIF_REG_LP_MODE_MASK) |\ ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ & EMIF_REG_DPD_EN_MASK))\