From patchwork Sat Mar 5 12:05:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 592367 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7DD0714076E for ; Sat, 5 Mar 2016 23:09:48 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C00D8A76A9; Sat, 5 Mar 2016 13:09:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CPZVe76tGh2E; Sat, 5 Mar 2016 13:09:28 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1B31A76BB; Sat, 5 Mar 2016 13:09:18 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27804A768E for ; Sat, 5 Mar 2016 13:09:10 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2XOro8koQchn for ; Sat, 5 Mar 2016 13:09:10 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 06E59A7695 for ; Sat, 5 Mar 2016 13:09:06 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u25C95mF026044; Sat, 5 Mar 2016 06:09:05 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u25C95oP005195; Sat, 5 Mar 2016 06:09:05 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Sat, 5 Mar 2016 06:09:04 -0600 Received: from a0131933.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u25C8sDB001789; Sat, 5 Mar 2016 06:09:03 -0600 From: Lokesh Vutla To: , Date: Sat, 5 Mar 2016 17:35:16 +0530 Message-ID: <1457179518-1177-5-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1457179518-1177-1-git-send-email-lokeshvutla@ti.com> References: <1457179518-1177-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Cc: Tero Kristo , Sekhar Nori Subject: [U-Boot] [PATCH 4/6] ARM: DRA7: EMIF: Add 4GB DDR settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- board/ti/dra7xx/evm.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index c493c64..d142ccc 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -34,6 +34,8 @@ #define board_is_dra74x_evm() board_ti_is("5777xCPU") #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ (strncmp("H", board_ti_get_rev(), 1) <= 0) +#define board_ti_get_emif_size() board_ti_get_emif1_size() + \ + board_ti_get_emif2_size() #ifdef CONFIG_DRIVER_TI_CPSW #include @@ -125,18 +127,78 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_rd_wr_exec_thresh = 0x00000305 }; +const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x30BF7FDA, + .sdram_tim3 = 0x427F8BA8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + switch (omap_revision()) { case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: switch (emif_nr) { case 1: - *regs = &emif1_ddr3_532_mhz_1cs; + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *regs = &emif1_ddr3_532_mhz_1cs_2G; + else + *regs = &emif1_ddr3_532_mhz_1cs; break; case 2: - *regs = &emif2_ddr3_532_mhz_1cs; + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *regs = &emif2_ddr3_532_mhz_1cs_2G; + else + *regs = &emif2_ddr3_532_mhz_1cs; break; } break; @@ -164,13 +226,28 @@ static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { .is_ma_present = 0x1 }; +const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + switch (omap_revision()) { case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: - *dmm_lisa_regs = &lisa_map_dra7_1536MB; + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *dmm_lisa_regs = &lisa_map_dra7_2GB; + else + *dmm_lisa_regs = &lisa_map_dra7_1536MB; break; case DRA722_ES1_0: default: