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BN3PR03MB1495; 5:6ISJHiL2UZXcFQdmc4uMXc3T+ka5hq5Tvd4+R0T5ezn9otY3oohxxdQl3ekpbCjI1G0NqulQoojNFAU+QW2+eeauxhcKHH3+29yp/w8679CbSom8sSVBHQjA0notQ1os21cn51s5JVZpUWxuaOYfbInn7Y1aLZjiQiyGMUb7XaE=; 24:fUa+7LgikwGLUd/5vRC2LDQS8OudJG72T7VrIbaiygfnhRBJpQyJvQ64eWZdTKVaMGU2QYgdZvCTRTyJtPpRf3nGK0Q4DEZYzjmVl1pTZig= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2016 15:46:24.7048 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1495 X-Mailman-Approved-At: Mon, 22 Feb 2016 17:16:20 +0100 Cc: marc.zyngier@arm.com, Stuart Yoder , leoyang.li@nxp.com, mingkai.hu@nxp.com Subject: [U-Boot] [PATCH 2/7] armv8: ls2080a: update stream ID partitioning info X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stuart Yoder -update comments around how stream IDs are partitioned -stream IDs allocated to PCI are no longer divided up by controller, but are instead a contiguous range Signed-off-by: Stuart Yoder --- .../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 55 ++++++++++++-------- 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h index 954104b..ee28323 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h @@ -7,28 +7,48 @@ #ifndef __FSL_STREAM_ID_H #define __FSL_STREAM_ID_H -/* Stream IDs on ls2080a devices are not hardwired and are +/* + * Stream IDs on ls2080a devices are not hardwired and are * programmed by sw. There are a limited number of stream IDs * available, and the partitioning of them is scenario dependent. * This header defines the partitioning between legacy, PCI, * and DPAA2 devices. * - * This partitiong can be customized in this file depending - * on the specific hardware config-- e.g. perhaps not all - * PEX controllers are in use. + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) * - * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for + * -DPAA2 + * -u-boot will allocate a range of stream IDs to be used by the Management + * Complex for containers and will set these values in the MC DPC image. + * -the MC is responsible for allocating and setting up 'isolation context + * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. + * + * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit * --------------------------- - * PL[18] 9 - * BMT[17] 8 - * VA[16] 7 - * [15] - - * ICID[14:7] - - * ICID[6:0] 6-0 + * PL[18] 9 // privilege bit + * BMT[17] 8 // bypass translation + * VA[16] 7 // reserved + * [15] - // unused + * ICID[14:7] - // unused + * ICID[6:0] 6-0 // isolation context id * ---------------------------- + * */ #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ @@ -46,16 +66,9 @@ #define FSL_SATA2_STREAM_ID 5 #define FSL_DMA_STREAM_ID 6 -/* PCI - programmed in PEXn_LUT by OS */ -/* 4 IDs per controller */ -#define FSL_PEX1_STREAM_ID_START 7 -#define FSL_PEX1_STREAM_ID_END 10 -#define FSL_PEX2_STREAM_ID_START 11 -#define FSL_PEX2_STREAM_ID_END 14 -#define FSL_PEX3_STREAM_ID_START 15 -#define FSL_PEX3_STREAM_ID_END 18 -#define FSL_PEX4_STREAM_ID_START 19 -#define FSL_PEX4_STREAM_ID_END 22 +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 7 +#define FSL_PEX_STREAM_ID_END 22 /* DPAA2 - set in MC DPC and alloced by MC */ #define FSL_DPAA2_STREAM_ID_START 23