From patchwork Sun Jan 17 23:11:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 569344 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AE21A140662 for ; Mon, 18 Jan 2016 10:14:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=C9bLpvv0; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76796A781F; Mon, 18 Jan 2016 00:13:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tMLNRAOfOhUE; Mon, 18 Jan 2016 00:13:21 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8879AA7820; Mon, 18 Jan 2016 00:12:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 878844BFB6 for ; Mon, 18 Jan 2016 00:12:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xL8LSt26cFRV for ; Mon, 18 Jan 2016 00:12:36 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f174.google.com (mail-ob0-f174.google.com [209.85.214.174]) by theia.denx.de (Postfix) with ESMTPS id 1B934A7553 for ; Mon, 18 Jan 2016 00:12:32 +0100 (CET) Received: by mail-ob0-f174.google.com with SMTP id vt7so149681074obb.1 for ; Sun, 17 Jan 2016 15:12:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=xKEWhsG+fQWcKp7p2QpGNf2bpcJtQsrtf34jda4BvaA=; b=C9bLpvv0RRFZ/UzZiiVJxtWf788QtKNqOWHfG5NjNHfImkCo1mSnMWnCoywlpaNzXL Dhn7PeFIvSG2AqqfoQmYH+u2r/otRR7+ACj0v96FIU6cWFDkfgHCO7WFR1c9e4Uu80ib K1Vx21RCJ8QMwPSTaDdEo6quKl/OLTOWyu0kfAwol5PifkekyHZx9Ei9y+fo7k1MXegy muZZZNAABoMHcVR4WC9zK/4pJRC9NX1fcpzTYQ5jdSbmkGHkV/oaoL/AqhRfzeZ76VWz Vpl46AasyyxfIoLbrJxA/6afAUVsCo/ADSsp+NDG5rDH/iIBH26xPBaOLaPkUT2tPlT4 Ls5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=xKEWhsG+fQWcKp7p2QpGNf2bpcJtQsrtf34jda4BvaA=; b=L+NFLscgqYWoO5FfAdbA5NID8LXzLRosQygg9Rd5YdF7wNdLlpQrsso7oxpXIhoYVA NmQwFF9yKI/3sKWeWutJtA8YwnU5sPVURdRc4OqO1nmeXFTGJ852U2OL4rYTZBajfsZH qZOGzGve9E15b9g0PFYZOkL59J9whNKyfTZ+LU3gcp9gLxnq0WboC/dxNHcx1b5kGgbs nGAKBMhgUgfggsVkS1fi2bdGlMMtInc3roxuBepeFrwa4xShU8OMcIrr5XTZHjvRf/4E gjy/ciIHq1qFEQyr99wd3U7khNpbk+qFIBPapipc9jVZhLadaL0lWn1uQfoac3AMenQi W24g== X-Gm-Message-State: AG10YORfwrHzWJkamegfU00jR0FYOPZNKCivnTUAmZRe/2iLJ9ZbR+nOtM29GNpb9N2BdMxx X-Received: by 10.60.60.39 with SMTP id e7mr5392120oer.20.1453072350822; Sun, 17 Jan 2016 15:12:30 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id r9sm11722310oih.6.2016.01.17.15.12.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 17 Jan 2016 15:12:29 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id A2E652211C5; Sun, 17 Jan 2016 16:12:26 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Sun, 17 Jan 2016 16:11:11 -0700 Message-Id: <1453072320-24298-7-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1453072320-24298-1-git-send-email-sjg@chromium.org> References: <1453072320-24298-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v2 06/55] x86: ivybridge: Move lpc_early_init() to probe() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: - Drop unused 'gen-dec' device tree property arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- arch/x86/dts/chromebook_link.dts | 3 +-- arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- 4 files changed, 26 insertions(+), 28 deletions(-) diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 6ffc843..4c6ffb2 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -124,10 +124,8 @@ int arch_cpu_init(void) int arch_cpu_init_dm(void) { - const void *blob = gd->fdt_blob; struct pci_controller *hose; struct udevice *bus, *dev; - int node; int ret; post_code(0x70); @@ -145,13 +143,6 @@ int arch_cpu_init_dm(void) if (!dev) return -ENODEV; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); - if (ret) - return ret; - enable_spi_prefetch(hose, PCH_LPC_DEV); /* This is already done in start.S, but let's do it in C */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 51a4073..9d089c7 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -454,7 +454,13 @@ static void pch_fixups(pci_dev_t dev) setbits_le32(RCB_REG(0x21a8), 0x3); } -int lpc_early_init(const void *blob, int node, pci_dev_t dev) +/** + * lpc_early_init() - set up LPC serial ports and other early things + * + * @dev: LPC device + * @return 0 if OK, -ve on error + */ +static int lpc_early_init(struct udevice *dev) { struct reg_info { u32 base; @@ -463,17 +469,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) int count; int i; - count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", - (u32 *)values, sizeof(values) / sizeof(u32)); + count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, + "intel,gen-dec", (u32 *)values, + sizeof(values) / sizeof(u32)); if (count < 0) return -EINVAL; /* Set COM1/COM2 decode range */ - x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010); + dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010); /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - GAMEL_LPC_EN | COMA_LPC_EN); + dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + GAMEL_LPC_EN | COMA_LPC_EN); /* Write all registers but use 0 if we run out of data */ count = count * sizeof(u32) / sizeof(values[0]); @@ -482,7 +489,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) if (i < count) reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); - x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg); + dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); } return 0; @@ -561,6 +568,17 @@ void lpc_enable(pci_dev_t dev) static int bd82x6x_lpc_probe(struct udevice *dev) { + int ret; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + ret = lpc_early_init(dev); + if (ret) { + debug("%s: lpc_early_init() failed\n", __func__); + return ret; + } + return 0; } diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index d5c5bfd..f2db844 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -192,8 +192,6 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - gen-dec = <0x800 0xfc 0x900 0xfc>; - intel,gen-dec = <0x800 0xfc 0x900 0xfc>; intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 0x80 0x80 0x80 0x80>; intel,gpi-routing = <0 0 0 0 0 0 0 2 @@ -224,6 +222,7 @@ #address-cells = <1>; #size-cells = <0>; u-boot,dm-pre-reloc; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 31437c8..19cd7e5 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -473,14 +473,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); int lpc_init(struct pci_controller *hose, pci_dev_t dev); void lpc_enable(pci_dev_t dev); -/** - * lpc_early_init() - set up LPC serial ports and other early things - * - * @blob: Device tree blob - * @node: Offset of LPC node - * @dev: PCH PCI device containing the LPC - * @return 0 if OK, -ve on error - */ -int lpc_early_init(const void *blob, int node, pci_dev_t dev); - #endif