From patchwork Sun Jan 17 23:11:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 569385 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DBA5214090A for ; Mon, 18 Jan 2016 10:28:37 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=nyBVGtJ3; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 82F66B38D3; Mon, 18 Jan 2016 00:20:27 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tNkA1XrT33Jm; Mon, 18 Jan 2016 00:20:27 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 683ECB37D9; Mon, 18 Jan 2016 00:19:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DA73AA7887 for ; Mon, 18 Jan 2016 00:19:22 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ahrN5jw_rsra for ; Mon, 18 Jan 2016 00:19:22 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f169.google.com (mail-ob0-f169.google.com [209.85.214.169]) by theia.denx.de (Postfix) with ESMTPS id 05543A787D for ; Mon, 18 Jan 2016 00:19:02 +0100 (CET) Received: by mail-ob0-f169.google.com with SMTP id is5so149648436obc.0 for ; Sun, 17 Jan 2016 15:19:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=BHEN0vHnnUAcnymX7KmqZ9aoYM+k1ujOw1NxXHRBBVE=; b=nyBVGtJ3e6yfnalwwJCYGiqj9BOZlJX1jq7U0Ofc+hNJ9mVObL3c/s+n32UYrTB0AW NtNueecKZGoMBoKwFtwBxmz/jdnIgr+6Gr2JzdWFT8jVwSNbD+B3cR3dFFVsOZwOtRfU xU8gVpg+JakueWgGhjZ3l/LRpvKLHI6zdibQ52U9Tho7V1cdqg8UkAYF45OXyZnvNntU UBpoSE3x3ZbRZ3g9J/sOmi7TjF3hqqvFNEKal1WuDFu6cnmT21Q7GFQgBFzr0qsZxSQ9 /Pwiz+7jmgJFNAJz7WP6bhFJegAQMdRjalU6rMeB4kVACTg+jR0HjQ/WVSfNydc8P9Cz A56g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=BHEN0vHnnUAcnymX7KmqZ9aoYM+k1ujOw1NxXHRBBVE=; b=atGQ8cmezolN2albXrq+LIkW9WtsikUH4CO0IAyP2KTPElrhDZ/tmoY/YDfAUDEIXc JQexO303HrcLkg34k0bIfX5tLpTq5XdCP5ljZVVVAHmmQvDImfZQh0mp9d2XWoZxq8qf iWH7P9+rTYNviLptOoj+4HSim9IEf9FipBA5cMLBNhxlwFGGCavK4wgE2xkxmYcpVuEX u1cDUqjhXG3T2sFu+oy9QGCoouXGh13WvZ+QCx4LCPW/JL6tyifTBb3teS4e+J231MV3 DeuJCDInSFIdjW2hoe/fehVjlpjTyaYHZmkDQd3D7V4X1bOmuIOTT8hvzSQGkQMMj8hY UGcw== X-Gm-Message-State: ALoCoQlLzLHR0JVEhgP9bfqDtyHBnTd3r8BKdVrsMcX3Z4f7VdvPw5oqhE1AuL3HvFftJSvOoVsCtrQZdj8TCYk2NxeRvwXiaA== X-Received: by 10.60.233.132 with SMTP id tw4mr17799850oec.35.1453072741448; Sun, 17 Jan 2016 15:19:01 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id s7sm11824766obk.17.2016.01.17.15.18.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 17 Jan 2016 15:18:58 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 88E5A220E3B; Sun, 17 Jan 2016 16:12:28 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Sun, 17 Jan 2016 16:11:27 -0700 Message-Id: <1453072320-24298-23-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1453072320-24298-1-git-send-email-sjg@chromium.org> References: <1453072320-24298-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v2 22/55] x86: ivybridge: Move early init code into northbridge.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: None arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/early_init.c | 81 ------------------------------------ arch/x86/cpu/ivybridge/northbridge.c | 67 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 82 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efae..bdbd3fa 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,6 @@ obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o -obj-y += early_init.o obj-y += early_me.o obj-y += gma.o obj-y += lpc.o diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c deleted file mode 100644 index 5b16abc..0000000 --- a/arch/x86/cpu/ivybridge/early_init.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * From Coreboot - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static void sandybridge_setup_northbridge_bars(struct udevice *dev) -{ - /* Set up all hardcoded northbridge BARs */ - debug("Setting up static registers\n"); - dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); - dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); - dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - /* 64MB - busses 0-63 */ - dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - dm_pci_write_config32(dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); - dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - dm_pci_write_config8(dev, PAM0, 0x30); - dm_pci_write_config8(dev, PAM1, 0x33); - dm_pci_write_config8(dev, PAM2, 0x33); - dm_pci_write_config8(dev, PAM3, 0x33); - dm_pci_write_config8(dev, PAM4, 0x33); - dm_pci_write_config8(dev, PAM5, 0x33); - dm_pci_write_config8(dev, PAM6, 0x33); -} - -static int bd82x6x_northbridge_probe(struct udevice *dev) -{ - const int chipset_type = SANDYBRIDGE_MOBILE; - u32 capid0_a; - u8 reg8; - - if (gd->flags & GD_FLG_RELOC) - return 0; - - /* Device ID Override Enable should be done very early */ - dm_pci_read_config32(dev, 0xe4, &capid0_a); - if (capid0_a & (1 << 10)) { - dm_pci_read_config8(dev, 0xf3, ®8); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - dm_pci_write_config8(dev, 0xf3, reg8); - } - - sandybridge_setup_northbridge_bars(dev); - - /* Device Enable */ - dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - return 0; -} - -static const struct udevice_id bd82x6x_northbridge_ids[] = { - { .compatible = "intel,bd82x6x-northbridge" }, - { } -}; - -U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { - .name = "bd82x6x_northbridge", - .id = UCLASS_NORTHBRIDGE, - .of_match = bd82x6x_northbridge_ids, - .probe = bd82x6x_northbridge_probe, -}; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e3d8c13..6b00d31 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -170,3 +171,69 @@ void northbridge_init(pci_dev_t dev) void northbridge_enable(pci_dev_t dev) { } + +static void sandybridge_setup_northbridge_bars(struct udevice *dev) +{ + /* Set up all hardcoded northbridge BARs */ + debug("Setting up static registers\n"); + dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); + dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + /* 64MB - busses 0-63 */ + dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + dm_pci_write_config32(dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); + dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + dm_pci_write_config8(dev, PAM0, 0x30); + dm_pci_write_config8(dev, PAM1, 0x33); + dm_pci_write_config8(dev, PAM2, 0x33); + dm_pci_write_config8(dev, PAM3, 0x33); + dm_pci_write_config8(dev, PAM4, 0x33); + dm_pci_write_config8(dev, PAM5, 0x33); + dm_pci_write_config8(dev, PAM6, 0x33); +} + +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, ®8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + + sandybridge_setup_northbridge_bars(dev); + + /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + + return 0; +} + +static const struct udevice_id bd82x6x_northbridge_ids[] = { + { .compatible = "intel,bd82x6x-northbridge" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { + .name = "bd82x6x_northbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = bd82x6x_northbridge_ids, + .probe = bd82x6x_northbridge_probe, +};