From patchwork Sun Jan 17 23:11:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 569364 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6AF8D14090A for ; Mon, 18 Jan 2016 10:21:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=eM4XUoEk; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 71D56B37F2; Mon, 18 Jan 2016 00:15:08 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tEhk6U0gjghq; Mon, 18 Jan 2016 00:15:08 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C229CB387E; Mon, 18 Jan 2016 00:13:34 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 98897A74E9 for ; Mon, 18 Jan 2016 00:12:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aMamoVcwz5b8 for ; Mon, 18 Jan 2016 00:12:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f50.google.com (mail-oi0-f50.google.com [209.85.218.50]) by theia.denx.de (Postfix) with ESMTPS id 19355A7811 for ; Mon, 18 Jan 2016 00:12:36 +0100 (CET) Received: by mail-oi0-f50.google.com with SMTP id k206so166441695oia.1 for ; Sun, 17 Jan 2016 15:12:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=XmWg0CCE2eH/5fklaFoA/UVTPsSiQqMXqLm8MG/fNx0=; b=eM4XUoEkFnCXdq9bANJgRj6PKe+gh65gbeL+wws2pRTG+N35gaxOjWWstnvcAOkCSi qu43YIx8u+KC5HNA/1eAuNO3Hq1y26EuDbUo3cQV0U4x90PkIXGwvBzPTKUVZlvI6w51 MV85E39arG9O3dUI77HiEfjygNr9P+GuVzGa+kX4mKld/9KjSft3kmMFTGq/wm06qKin aImbz19dB8I7Of2XUWnEvHJtgg29jg/6iFtQzz+SJ3SGQ+68vV0spXNpIOnuJq5k/tMS 9jGwpp0TVikLhuDIO3KodqqQegbxSW/iUYjxg8U96oH36rkjvN/d4Ygm7csbFEftbGcj 3DvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=XmWg0CCE2eH/5fklaFoA/UVTPsSiQqMXqLm8MG/fNx0=; b=DoE2gu5tdXCu1RlFoxFBJv7dUNOhEvscQXN9yjEr7WvE0V2qw12WNHDLYzNltiWIwH W0SrqgBPE/nd1NQ6uwrIz/HcIBfcU48fwOjNVBxXpNp/uE0AxMTCRH3s8bIWzjc64A0d Om6dg04zPUHfHQGqioXVYd0eYIqnzuUA3lvv3KDULmr849UwLTkqM0bXTRnnq/L73yqq +3kP67UTDT4bPLZhknk+YByBq3FPWR3WLx2dGKCx96Q7PdS50py77mCia1jEv+b/9Jpt hbLHBvhejy++59PAnioBDGarB7C/yWgAopgwPP61w1ty5hUrXeI577vyr2A+FvurznHT rjxQ== X-Gm-Message-State: ALoCoQnPN2Eto/1/65WhFGh/mqPcpC1x0osBGV4dPWhFIIWkg+lkrYnR+AXrdXRwqZjKqXmasZr8ryI4cfCLnLe6PNB7YSkYDQ== X-Received: by 10.202.68.84 with SMTP id r81mr15313677oia.41.1453072355017; Sun, 17 Jan 2016 15:12:35 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id y9sm11797012obg.4.2016.01.17.15.12.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 17 Jan 2016 15:12:32 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id CABE422167C; Sun, 17 Jan 2016 16:12:27 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Sun, 17 Jan 2016 16:11:20 -0700 Message-Id: <1453072320-24298-16-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1453072320-24298-1-git-send-email-sjg@chromium.org> References: <1453072320-24298-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v2 15/55] x86: ivybridge: Move graphics init much later X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: None arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/ivybridge/early_init.c | 80 ++----------------------------------- arch/x86/cpu/ivybridge/gma.c | 73 +++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 78 deletions(-) diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 65eea1f..c3626c4 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -250,7 +250,6 @@ int print_cpuinfo(void) return ret; if (!dev) return -ENODEV; - sandybridge_early_init(SANDYBRIDGE_MOBILE); /* Check PM1_STS[15] to see if we are waking from Sx */ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 029f5ef..83ef7b7 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -53,83 +53,6 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); } -static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) -{ - u32 reg32; - u16 reg16; - u8 reg8; - - reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID); - switch (reg16) { - case 0x0102: /* GT1 Desktop */ - case 0x0106: /* GT1 Mobile */ - case 0x010a: /* GT1 Server */ - case 0x0112: /* GT2 Desktop */ - case 0x0116: /* GT2 Mobile */ - case 0x0122: /* GT2 Desktop >=1.3GHz */ - case 0x0126: /* GT2 Mobile >=1.3GHz */ - case 0x0156: /* IvyBridge */ - case 0x0166: /* IvyBridge */ - break; - default: - debug("Graphics not supported by this CPU/chipset\n"); - return; - } - - debug("Initialising Graphics\n"); - - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ - reg16 = x86_pci_read_config16(pch_dev, GGC); - reg16 &= ~0x00f8; - reg16 |= 1 << 3; - /* Program GTT memory by setting GGC[9:8] = 2MB */ - reg16 &= ~0x0300; - reg16 |= 2 << 8; - /* Enable VGA decode */ - reg16 &= ~0x0002; - x86_pci_write_config16(pch_dev, GGC, reg16); - - /* Enable 256MB aperture */ - reg8 = x86_pci_read_config8(video_dev, MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - x86_pci_write_config8(video_dev, MSAC, reg8); - - /* Erratum workarounds */ - reg32 = readl(MCHBAR_REG(0x5f00)); - reg32 |= (1 << 9) | (1 << 10); - writel(reg32, MCHBAR_REG(0x5f00)); - - /* Enable SA Clock Gating */ - reg32 = readl(MCHBAR_REG(0x5f00)); - writel(reg32 | 1, MCHBAR_REG(0x5f00)); - - /* GPU RC6 workaround for sighting 366252 */ - reg32 = readl(MCHBAR_REG(0x5d14)); - reg32 |= (1 << 31); - writel(reg32, MCHBAR_REG(0x5d14)); - - /* VLW */ - reg32 = readl(MCHBAR_REG(0x6120)); - reg32 &= ~(1 << 0); - writel(reg32, MCHBAR_REG(0x6120)); - - reg32 = readl(MCHBAR_REG(0x5418)); - reg32 |= (1 << 4) | (1 << 5); - writel(reg32, MCHBAR_REG(0x5418)); -} - -void sandybridge_early_init(int chipset_type) -{ - pci_dev_t pch_dev = PCH_DEV; - pci_dev_t video_dev = PCH_VIDEO_DEV; - - /* Device Enable */ - x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - sandybridge_setup_graphics(pch_dev, video_dev); -} - static int bd82x6x_northbridge_probe(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; @@ -155,6 +78,9 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) sandybridge_setup_northbridge_bars(dev); + /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + return 0; } diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 85a09c6..1748f7f 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -728,16 +729,88 @@ static int int15_handler(void) return res; } +void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ + break; + default: + debug("Graphics not supported by this CPU/chipset\n"); + return; + } + + debug("Initialising Graphics\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + dm_pci_read_config16(dev, GGC, ®16); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + dm_pci_write_config16(dev, GGC, reg16); + + /* Enable 256MB aperture */ + dm_pci_read_config8(video_dev, MSAC, ®8); + reg8 &= ~0x06; + reg8 |= 0x02; + dm_pci_write_config8(video_dev, MSAC, reg8); + + /* Erratum workarounds */ + reg32 = readl(MCHBAR_REG(0x5f00)); + reg32 |= (1 << 9) | (1 << 10); + writel(reg32, MCHBAR_REG(0x5f00)); + + /* Enable SA Clock Gating */ + reg32 = readl(MCHBAR_REG(0x5f00)); + writel(reg32 | 1, MCHBAR_REG(0x5f00)); + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = readl(MCHBAR_REG(0x5d14)); + reg32 |= (1 << 31); + writel(reg32, MCHBAR_REG(0x5d14)); + + /* VLW */ + reg32 = readl(MCHBAR_REG(0x6120)); + reg32 &= ~(1 << 0); + writel(reg32, MCHBAR_REG(0x6120)); + + reg32 = readl(MCHBAR_REG(0x5418)); + reg32 |= (1 << 4) | (1 << 5); + writel(reg32, MCHBAR_REG(0x5418)); +} + int gma_func0_init(struct udevice *dev, const void *blob, int node) { #ifdef CONFIG_VIDEO ulong start; #endif + struct udevice *nbridge; void *gtt_bar; ulong base; u32 reg32; int ret; + ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); + if (!nbridge) + return -ENODEV; + sandybridge_setup_graphics(nbridge, dev); + /* IGD needs to be Bus Master */ dm_pci_read_config32(dev, PCI_COMMAND, ®32); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;