@@ -38,6 +38,7 @@
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_SMMU3_ADDR (CONFIG_SYS_IMMR + 0x300000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
@@ -6,6 +6,39 @@
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#define CONFIG_SMMU_NSCR_OFFSET 0x400
+#define CONFIG_SMMU_SMR_OFFSET 0x800
+#define CONFIG_SMMU_S2CR_OFFSET 0xc00
+
+#define SMMU_NSCR_CLIENTPD_SHIFT 0
+#define SMMU_NSCR_MTCFG_SHIFT 20
+
+#define SMR_SMR_VALID_SHIFT 31
+#define SMR_ID_MASK 0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT 22
+#define S2CR_WACFG_MASK 0x3
+#define S2CR_WACFG_WRITE_ALLOCATE 0x2
+
+#define S2CR_RACFG_SHIFT 20
+#define S2CR_RACFG_MASK 0x3
+#define S2CR_RACFG_READ_ALLOCATE 0x2
+
+#define S2CR_TYPE_SHIFT 16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS 0x01
+
+#define S2CR_MEM_ATTR_SHIFT 12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE 0xa
+
+#define S2CR_MTCFG 0x00000800
+
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK 0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
#include <fsl_sec.h>
@@ -71,4 +104,5 @@ struct smmu_stream_id {
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu3(uint32_t liodn);
#endif
@@ -20,7 +20,7 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
{
int i;
- u32 liodn;
+ uint32_t liodn;
for (i = 0; i < size; i++) {
if (tbl[i].num_ids == 2)
@@ -31,3 +31,37 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
}
}
+
+void ls1021x_config_smmu3(uint32_t liodn)
+{
+ uint32_t *addr;
+ uint32_t smr, s2cr, nscr;
+
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_NSCR_OFFSET);
+ /* SMMU NSCR configuration */
+ nscr = in_le32(addr);
+
+ nscr = nscr & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
+ 1 << SMMU_NSCR_MTCFG_SHIFT);
+ out_le32(addr, nscr);
+
+ /* SMMU SMR configuration */
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_SMR_OFFSET);
+
+ smr = 0;
+ smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
+ smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
+
+ out_le32(addr, smr);
+
+ /* SMMU S2CR configuration */
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_S2CR_OFFSET);
+ s2cr = (S2CR_WACFG_WRITE_ALLOCATE << S2CR_WACFG_SHIFT) |
+ (S2CR_RACFG_READ_ALLOCATE << S2CR_RACFG_SHIFT) |
+ (S2CR_TYPE_BYPASS << S2CR_TYPE_SHIFT) |
+ (S2CR_MEM_ATTR_CACHEABLE << S2CR_MEM_ATTR_SHIFT) |
+ S2CR_MTCFG |
+ (S2CR_SHCFG_OUTER_CACHEABLE << S2CR_SHCFG_SHIFT);
+
+ out_le32(addr, s2cr);
+}
@@ -481,6 +481,10 @@ int board_init(void)
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
+ /* Configure SMMU3 to make transactions with CAAM stream ID
+ * as cacheable
+ */
+ ls1021x_config_smmu3(0x10);
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
@@ -528,6 +528,10 @@ int board_init(void)
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
+ /* Configure SMMU3 to make transactions with CAAM stream ID
+ * as cacheable
+ */
+ ls1021x_config_smmu3(0x10);
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();