From patchwork Sat Jan 16 23:44:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 569186 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E697A140B98 for ; Sun, 17 Jan 2016 10:46:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=hNU19FG8; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6563CA7766; Sun, 17 Jan 2016 00:45:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id e3tmOnXYlTN5; Sun, 17 Jan 2016 00:45:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8101CA7806; Sun, 17 Jan 2016 00:45:24 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34AB8A778F for ; Sun, 17 Jan 2016 00:45:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4X_XPLHjmeSQ for ; Sun, 17 Jan 2016 00:45:09 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f171.google.com (mail-ob0-f171.google.com [209.85.214.171]) by theia.denx.de (Postfix) with ESMTPS id 229A5A77B9 for ; Sun, 17 Jan 2016 00:45:00 +0100 (CET) Received: by mail-ob0-f171.google.com with SMTP id ba1so548342396obb.3 for ; Sat, 16 Jan 2016 15:45:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=s7n/kBt9Mvl52gaSaYXV3yqMEZls7GRVGB6eEyDUBZ4=; b=hNU19FG8rUthAzHBC3yD5n96LR+81LNqIbR4QIT0iI/b0ybo9n5ZQvoz3698l7mhUQ +VaPzndnJF4wlddUOwvwqe6dSwMbiKdP1tyhUPMPt5u4shZwedN6Ka2gRQKdwpSy8tbj fdjbYZ44QlvLYiEHvNSRJpntNT9qQVC12Wm8DQ6kSgkgK2/81t1N8CQAkVIcqzuA8RxL XXzVprNTqaRIhYPMAScIZg2DZaNxMBtMUQWUs3zJo5okMrb6HPogY+JlordvkQhJvz7D H87/6SRoUvtTYeQBROdbEcPG8naX/sbRYYpajRjpjuH+OH75k21XEOsU4loadzIPeLqb 5POA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=s7n/kBt9Mvl52gaSaYXV3yqMEZls7GRVGB6eEyDUBZ4=; b=Zb/L8sYB6f/rQ+FBUy+6jVuHA5aGtPiM7WeTb4Ag+CrqiLESJarNSypShL+Tt7Y3L5 uFgnOaNwNcAD51WOkCkCewRzO5O6JXZyF1FJ3yqBiWiUmnychaR2T/cFMhpUFfWxEGmV L0Vbfo3cvPuLzyzTOUQT4TZDUevEQP9uy7669kMFJtOy3+TY7J3BVnT01hOtptwxWUnb Gf4JkNo0k1ryoT0ybqEWLPFaDAypvK+mHe0vfTYXJhELk1U/aYDC4STxSNnFN1ZU8TPX eGyiJ9dWCFjWpw8anHWnbVU3X2RU0wtYvBOK3b9Bq9BJ1eOw38w0UbjTEJ4b8S7nq01j aFiw== X-Gm-Message-State: ALoCoQlpxCvMlYSzfLyNlZb4FhgnmbAqBab4LxVJ6VcfgisR8q2RIHbwgAUVbbbVwtJS2SMV+V2IRxLmcSonTZDdJtNW2rLtOQ== X-Received: by 10.60.67.166 with SMTP id o6mr13661698oet.77.1452987899083; Sat, 16 Jan 2016 15:44:59 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id m2sm9640671oia.7.2016.01.16.15.44.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 16 Jan 2016 15:44:57 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 53370221993; Sat, 16 Jan 2016 16:44:56 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Sat, 16 Jan 2016 16:44:42 -0700 Message-Id: <1452987885-21970-6-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1452987885-21970-1-git-send-email-sjg@chromium.org> References: <1452987885-21970-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v4 5/8] dm: x86: Add a driver for Intel PCH7 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: - Correct BIOS_CTRL address for PCH7 Changes in v3: None Changes in v2: - Rename the PCH functions - Update the get_version() handle to use an enum - Add a function to obtain the SPI base address - Add enums for BIOS_CTRL register and bits drivers/pch/Makefile | 1 + drivers/pch/pch7.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++ include/pch.h | 8 +++++++ 3 files changed, 70 insertions(+) create mode 100644 drivers/pch/pch7.c diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index d69a99c..33aa727 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -3,3 +3,4 @@ # obj-y += pch-uclass.o +obj-y += pch7.o diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c new file mode 100644 index 0000000..ef72422 --- /dev/null +++ b/drivers/pch/pch7.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define BIOS_CTRL 0xd8 + +static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3020; + + return 0; +} + +static enum pch_version pch7_get_version(struct udevice *dev) +{ + return PCHV_7; +} + +static int pch7_set_spi_protect(struct udevice *dev, bool protect) +{ + uint8_t bios_cntl; + + /* Adjust the BIOS write protect to dis/allow write commands */ + dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); + if (protect) + bios_cntl &= ~BIOS_CTRL_BIOSWE; + else + bios_cntl |= BIOS_CTRL_BIOSWE; + dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); + + return 0; +} + +static const struct pch_ops pch7_ops = { + .get_sbase = pch7_get_sbase, + .get_version = pch7_get_version, + .set_spi_protect = pch7_set_spi_protect, +}; + +static const struct udevice_id pch7_ids[] = { + { .compatible = "intel,pch7" }, + { } +}; + +U_BOOT_DRIVER(pch7_drv) = { + .name = "intel-pch7", + .id = UCLASS_PCH, + .of_match = pch7_ids, + .ops = &pch7_ops, +}; diff --git a/include/pch.h b/include/pch.h index ff26865..dbfa265 100644 --- a/include/pch.h +++ b/include/pch.h @@ -14,6 +14,14 @@ enum pch_version { PCHV_9, }; +enum { + PCH_RCBA = 0xf0, +}; + +enum { + BIOS_CTRL_BIOSWE = BIT(0), +}; + /* Operations for the Platform Controller Hub */ struct pch_ops { /**