From patchwork Thu Jan 14 15:57:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 567546 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 17B6F140C0D for ; Fri, 15 Jan 2016 03:00:01 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=OXacqXSF; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B32DEA7781; Thu, 14 Jan 2016 16:59:32 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q8TAEKn6OPDi; Thu, 14 Jan 2016 16:59:32 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 64E4AA7711; Thu, 14 Jan 2016 16:59:08 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CAE08A75B7 for ; Thu, 14 Jan 2016 16:58:43 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Vic7SdhjqWUb for ; Thu, 14 Jan 2016 16:58:43 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f181.google.com (mail-ob0-f181.google.com [209.85.214.181]) by theia.denx.de (Postfix) with ESMTPS id 046A1A764F for ; Thu, 14 Jan 2016 16:58:37 +0100 (CET) Received: by mail-ob0-f181.google.com with SMTP id py5so118786090obc.2 for ; Thu, 14 Jan 2016 07:58:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ta0yps7pRWLhWCt5VNiqZClYf+xdL8ddt4eaUMPA64w=; b=OXacqXSFWBaTTe6dShhMja/fGgAlyrorN8tZnhmdgNqW5XQEXvnM6wsVJNsXGJok8n /raehShkm1T9OnvInkoSNDIA4KUV89xzOvM/noC2cb+MqVY6ZPv1VbLVIxb8/T25Qkc1 xefEAxlRd86v5E/eVnTySCptuxIkLcOLplv0c38koo2Ye4NPEgS76KSeJV3+Zc1XETKa JcLaEDuHX5QMT5KL0FbKVpg3R55ngVPzk5ihn1Vh+8+v8JvV1hMC5xwLcFZYR8gLiuL3 0AdYqMOuvS0jV7u3SX7VuOrdBeeS2oR8LsvAow1U9gamShJJoaFd9TvXywBeLE0EhW+R Eg0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ta0yps7pRWLhWCt5VNiqZClYf+xdL8ddt4eaUMPA64w=; b=H2Hz60xxw0BsHaklxS3ZEPzQWlBANYoY+ygmQV2QzG3qOewxPjaoLSgN3Vxafq1b2N 4WTc8RuDAMvXmmL3mdFbcGzNpNUJ8kdE29kvdxP7jFtcUnGNKpCzHVM9BBj7JtIsoTH4 z35pfL92IV/mYNBmQQ9i3ugiLI6KH8HU4CJaPTz0vQ1FezfQuxISZRrX9c1TivzZCz+m VZbd6AEDu8TdY+LKtIl4egL8H1U7FboQBW+Au1JQWGL+M8e9ZQwBZN2pSFjsoqVRit6t SHPnEAdRcLGNmFESAysfH7zRybOiublGeUtN17flh+mALho9eYq4BVrkROhhdWSzNTuh QlhA== X-Gm-Message-State: ALoCoQnKCw7GS8WmvTri33vi4L/HYsr/++wGWY9gn3L1ZrlC4WlpWZsFku/6fLuPxz3xdDyH7aLrAQCiWBjqQfihR1mL8tUHog== X-Received: by 10.60.16.198 with SMTP id i6mr4128229oed.19.1452787116118; Thu, 14 Jan 2016 07:58:36 -0800 (PST) Received: from kaki.bld.corp.google.com ([2620:0:1005:1100:d89c:e1e6:f7d3:3352]) by smtp.gmail.com with ESMTPSA id ur2sm3754219obc.11.2016.01.14.07.58.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jan 2016 07:58:35 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 65134221111; Thu, 14 Jan 2016 08:58:32 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 14 Jan 2016 08:57:50 -0700 Message-Id: <1452787100-21782-8-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1452787100-21782-1-git-send-email-sjg@chromium.org> References: <1452787100-21782-1-git-send-email-sjg@chromium.org> Cc: Tom Cubie , Jeffy Chen Subject: [U-Boot] [PATCH 07/37] pwm: rockchip: Add a PWM driver for Rockchip SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/pwm.h | 41 ++++++++++++ drivers/pwm/Kconfig | 9 +++ drivers/pwm/Makefile | 1 + drivers/pwm/rk_pwm.c | 103 +++++++++++++++++++++++++++++++ 4 files changed, 154 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/pwm.h create mode 100644 drivers/pwm/rk_pwm.c diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h new file mode 100644 index 0000000..08ff945 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/pwm.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2016 Google, Inc + * (C) Copyright 2008-2014 Rockchip Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_PWM_H +#define _ASM_ARCH_PWM_H + +struct rk3288_pwm { + u32 cnt; + u32 period_hpr; + u32 duty_lpr; + u32 ctrl; +}; +check_member(rk3288_pwm, ctrl, 0xc); + +#define RK_PWM_DISABLE (0 << 0) +#define RK_PWM_ENABLE (1 << 0) + +#define PWM_ONE_SHOT (0 << 1) +#define PWM_CONTINUOUS (1 << 1) +#define RK_PWM_CAPTURE (1 << 2) + +#define PWM_DUTY_POSTIVE (1 << 3) +#define PWM_DUTY_NEGATIVE (0 << 3) + +#define PWM_INACTIVE_POSTIVE (1 << 4) +#define PWM_INACTIVE_NEGATIVE (0 << 4) + +#define PWM_OUTPUT_LEFT (0 << 5) +#define PWM_OUTPUT_CENTER (1 << 5) + +#define PWM_LP_ENABLE (1 << 8) +#define PWM_LP_DISABLE (0 << 8) + +#define PWM_SEL_SCALE_CLK (1 << 9) +#define PWM_SEL_SRC_CLK (0 << 9) + +#endif diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index bd47159..cd8f357 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -8,3 +8,12 @@ config DM_PWM spends in the 'high' state, the higher the voltage. The PWM's frequency/period can be controlled along with the proportion of that time that the signal is high. + +config PWM_ROCKCHIP + bool "Enable support for the Rockchip PWM" + depends on DM_PWM + help + This PWM is found on RK3288 and other Rockchip SoCs. It supports a + programmable period and duty cycle. A 32-bit counter is used. + Various options provided in the hardware (such as capture mode and + continuous/single-shot) are not supported by the driver. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index d1b15e5..b6d8c16 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -11,4 +11,5 @@ #ccflags-y += -DDEBUG obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c new file mode 100644 index 0000000..2d289a4 --- /dev/null +++ b/drivers/pwm/rk_pwm.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rk_pwm_priv { + struct rk3288_pwm *regs; + struct rk3288_grf *grf; +}; + +static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, + uint duty_ns) +{ + struct rk_pwm_priv *priv = dev_get_priv(dev); + struct rk3288_pwm *regs = priv->regs; + unsigned long period, duty; + + debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns); + writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | + PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | + RK_PWM_DISABLE, + ®s->ctrl); + + period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000); + duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000); + + writel(period, ®s->period_hpr); + writel(duty, ®s->duty_lpr); + debug("%s: period=%lu, duty=%lu\n", __func__, period, duty); + + return 0; +} + +static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct rk_pwm_priv *priv = dev_get_priv(dev); + struct rk3288_pwm *regs = priv->regs; + + debug("%s: Enable '%s'\n", __func__, dev->name); + clrsetbits_le32(®s->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0); + + return 0; +} + +static int rk_pwm_ofdata_to_platdata(struct udevice *dev) +{ + struct rk_pwm_priv *priv = dev_get_priv(dev); + struct regmap *map; + + priv->regs = (struct rk3288_pwm *)dev_get_addr(dev); + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->grf = regmap_get_range(map, 0); + + return 0; +} + +static int rk_pwm_probe(struct udevice *dev) +{ + struct rk_pwm_priv *priv = dev_get_priv(dev); + + rk_setreg(&priv->grf->soc_con2, 1 << 0); + + return 0; +} + +static const struct pwm_ops rk_pwm_ops = { + .set_config = rk_pwm_set_config, + .set_enable = rk_pwm_set_enable, +}; + +static const struct udevice_id rk_pwm_ids[] = { + { .compatible = "rockchip,rk3288-pwm" }, + { } +}; + +U_BOOT_DRIVER(rk_pwm) = { + .name = "rk_pwm", + .id = UCLASS_PWM, + .of_match = rk_pwm_ids, + .ops = &rk_pwm_ops, + .ofdata_to_platdata = rk_pwm_ofdata_to_platdata, + .probe = rk_pwm_probe, + .priv_auto_alloc_size = sizeof(struct rk_pwm_priv), +};