From patchwork Mon Dec 28 09:18:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miao Yan X-Patchwork-Id: 561255 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4B1FF140BEB for ; Mon, 28 Dec 2015 20:19:00 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=VNrV6tD3; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE66C4B986; Mon, 28 Dec 2015 10:18:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id upwblNOhkDOH; Mon, 28 Dec 2015 10:18:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 857694B98A; Mon, 28 Dec 2015 10:18:57 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A08A64B95B for ; Mon, 28 Dec 2015 10:18:48 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ym2PDSZlUvBt for ; Mon, 28 Dec 2015 10:18:48 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f170.google.com (mail-pf0-f170.google.com [209.85.192.170]) by theia.denx.de (Postfix) with ESMTPS id 0716E4B950 for ; Mon, 28 Dec 2015 10:18:43 +0100 (CET) Received: by mail-pf0-f170.google.com with SMTP id e65so57998895pfe.1 for ; Mon, 28 Dec 2015 01:18:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=RWKmzZGlQwSyx08HDt3dCZ6McOtk4I3eVD/uUGnbJ5E=; b=VNrV6tD3GoOe7ENO1xxWK2ttTlT9/Cd3T8vxkmUIq+xDyq2zyoS9I05KEQCf3K0Jcy fD64aLY/pYtdIKcS8oM8inejBOjEZvAnw0BBE5KGbYpqMgjWA/ChAIUsmBkuwRH/9j+/ Blh2chnIVFUMXMLQA6UXfJlyMs7wBbwXA6d2Jwx5HT0DNauNY2tlIwc3u+9/o+3e6J87 FH+qLizFDw2CEsbkx/38tTymOuNMEDqjjMKeejRJeIMCNFSA02rQRK5skuTCv04yghnv 8TnvRZ4qyJyo6Lq4hxGHjCtYb7aCuPp7LJTl/D9hQK2cZpte9dGssC/nahW0/lg8o/h9 +BAA== X-Received: by 10.98.13.206 with SMTP id 75mr30114189pfn.101.1451294322446; Mon, 28 Dec 2015 01:18:42 -0800 (PST) Received: from pa-dbc1131.eng.vmware.com ([208.91.1.34]) by smtp.gmail.com with ESMTPSA id k65sm75037530pfj.57.2015.12.28.01.18.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Dec 2015 01:18:41 -0800 (PST) From: Miao Yan To: bmeng.cn@gmail.com, u-boot@lists.denx.de Date: Mon, 28 Dec 2015 01:18:26 -0800 Message-Id: <1451294312-53901-2-git-send-email-yanmiaobest@gmail.com> X-Mailer: git-send-email 2.6.3.444.gfd13a2e In-Reply-To: <1451294312-53901-1-git-send-email-yanmiaobest@gmail.com> References: <1451294312-53901-1-git-send-email-yanmiaobest@gmail.com> Subject: [U-Boot] [PATCH 1/7] x86: qemu: add fw_cfg support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The QEMU fw_cfg interface allows the guest to retrieve various data information from QEMU. For example, APCI/SMBios tables, number of online cpus, kernel data and command line, etc. This patch adds support for QEMU fw_cfg interface. Signed-off-by: Miao Yan --- arch/x86/cpu/qemu/Makefile | 2 +- arch/x86/cpu/qemu/fw_cfg.c | 215 +++++++++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/qemu/fw_cfg.h | 84 ++++++++++++++++++ arch/x86/cpu/qemu/qemu.c | 3 + 4 files changed, 303 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/qemu/fw_cfg.c create mode 100644 arch/x86/cpu/qemu/fw_cfg.h diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 3f3958a..ad424ec 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -7,5 +7,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif -obj-y += qemu.o +obj-y += qemu.o fw_cfg.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c new file mode 100644 index 0000000..e7615d1 --- /dev/null +++ b/arch/x86/cpu/qemu/fw_cfg.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "fw_cfg.h" + +static bool fwcfg_present; +static bool fwcfg_dma_present; + +static void qemu_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +static void qemu_fwcfg_read_entry_dma(uint16_t entry, + uint32_t length, void *address) +{ + struct fw_cfg_dma_access dma; + + debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", + address, length, dma.control); + + dma.length = cpu_to_be32(length); + dma.address = cpu_to_be64((uintptr_t)address); + dma.control = cpu_to_be32(FW_CFG_DMA_READ); + if (entry != FW_CFG_INVALID) + dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); + + barrier(); + + outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT + 4); + + while (dma.control & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("rep;nop"); +} + +static int qemu_fwcfg_present(void) +{ + uint32_t qemu; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; +} + +static int qemu_fwcfg_dma_present(void) +{ + uint8_t dma_enabled; + uint32_t qemu; + + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & 0x1) { + qemu = inl(FW_DMA_PORT); + if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE) + return 1; + } + return 0; +} + +static void qemu_fwcfg_read_entry(uint16_t entry, + uint32_t length, void *address) +{ + if (fwcfg_dma_present) + qemu_fwcfg_read_entry_dma(entry, length, address); + else + qemu_fwcfg_read_entry_pio(entry, length, address); +} + +uint16_t qemu_fwcfg_online_cpus(void) +{ + uint16_t nb_cpus; + if (!fwcfg_present) + return 1; + + qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); + return nb_cpus; +} + +static int qemu_fwcfg_setup_kernel(void *load_addr) +{ + char *cmd_addr; + uint32_t setup_size, kernel_size, cmdline_size, initrd_size; + + qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); + qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); + + if (setup_size == 0 || kernel_size == 0) { + printf("warning: no kernel available\n"); + return -1; + } + qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, setup_size, load_addr); + qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, kernel_size, + (char *)load_addr + setup_size); + + qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); + if (initrd_size == 0) { + printf("warning: no initrd available\n"); + } else { + qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, initrd_size, + (char *)load_addr + + setup_size + kernel_size); + } + + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); + cmd_addr = (char *)load_addr + setup_size + kernel_size + initrd_size; + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, cmdline_size, cmd_addr); + + printf("loading kernel to address %p", load_addr); + if (initrd_size) + printf(" initrd %p\n", + (char *)load_addr + setup_size + kernel_size); + else + printf("\n"); + + return setenv("bootargs", cmd_addr); +} + +static int qemu_fwcfg_list_firmware(void) +{ + int i; + uint32_t count; + struct fw_cfg_files *files; + + qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); + if (!count) + return 0; + + count = be32_to_cpu(count); + files = malloc(count * sizeof(struct fw_cfg_file)); + if (!files) + return -ENOMEM; + + files->count = count; + qemu_fwcfg_read_entry(FW_CFG_INVALID, + count * sizeof(struct fw_cfg_file), + files->files); + + for (i = 0; i < files->count; i++) + printf("%-56s\n", files->files[i].name); + free(files); + return 0; +} + +void qemu_fwcfg_init(void) +{ + fwcfg_present = false; + fwcfg_dma_present = false; + + if (qemu_fwcfg_present()) { + fwcfg_present = true; + if (qemu_fwcfg_dma_present()) + fwcfg_dma_present = true; + } +} + +int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + void *load_addr; + + if (!fwcfg_present) { + printf("no qemu fw_cfg found\n"); + return 0; + } + + if (!strncmp(argv[1], "list", 4)) { + qemu_fwcfg_list_firmware(); + return 0; + } else if (!strncmp(argv[1], "cpus", 4)) { + printf("%u\n", qemu_fwcfg_online_cpus()); + return 0; + } else if (!strncmp(argv[1], "load", 4)) { + if (argc == 3) { + load_addr = (void *)simple_strtoul(argv[2], NULL, 16); + } else { + load_addr = getenv("loadaddr"); + if (!load_addr) + load_addr = (void *)CONFIG_SYS_LOAD_ADDR; + else + load_addr = (void *)simple_strtoul(load_addr, + NULL, 16); + } + + return qemu_fwcfg_setup_kernel(load_addr); + + } else { + return -1; + } + + return 0; +} + +U_BOOT_CMD( + fw, 3, 1, do_qemu_fw, + "qemu firmware interface", + "\n" + " - list : print firmware(s) currently loaded\n" + " - cpus : print online cpu number\n" + " - load : load kernel (if any) to address , and setup for zboot\n" +) diff --git a/arch/x86/cpu/qemu/fw_cfg.h b/arch/x86/cpu/qemu/fw_cfg.h new file mode 100644 index 0000000..66e0c8a --- /dev/null +++ b/arch/x86/cpu/qemu/fw_cfg.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FW_CFG__ +#define __FW_CFG__ + +#include +#include + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT 0x514 + +#define FW_CFG_SIGNATURE 0x00 +#define FW_CFG_ID 0x01 +#define FW_CFG_UUID 0x02 +#define FW_CFG_RAM_SIZE 0x03 +#define FW_CFG_NOGRAPHIC 0x04 +#define FW_CFG_NB_CPUS 0x05 +#define FW_CFG_MACHINE_ID 0x06 +#define FW_CFG_KERNEL_ADDR 0x07 +#define FW_CFG_KERNEL_SIZE 0x08 +#define FW_CFG_KERNEL_CMDLINE 0x09 +#define FW_CFG_INITRD_ADDR 0x0a +#define FW_CFG_INITRD_SIZE 0x0b +#define FW_CFG_BOOT_DEVICE 0x0c +#define FW_CFG_NUMA 0x0d +#define FW_CFG_BOOT_MENU 0x0e +#define FW_CFG_MAX_CPUS 0x0f +#define FW_CFG_KERNEL_ENTRY 0x10 +#define FW_CFG_KERNEL_DATA 0x11 +#define FW_CFG_INITRD_DATA 0x12 +#define FW_CFG_CMDLINE_ADDR 0x13 +#define FW_CFG_CMDLINE_SIZE 0x14 +#define FW_CFG_CMDLINE_DATA 0x15 +#define FW_CFG_SETUP_ADDR 0x16 +#define FW_CFG_SETUP_SIZE 0x17 +#define FW_CFG_SETUP_DATA 0x18 +#define FW_CFG_FILE_DIR 0x19 + +#define FW_CFG_FILE_FIRST 0x20 +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS) + +#define FW_CFG_WRITE_CHANNEL 0x4000 +#define FW_CFG_ARCH_LOCAL 0x8000 +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) + +#define FW_CFG_INVALID 0xffff + +#define FW_CFG_MAX_FILE_PATH 56 + +#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') + +#define FW_CFG_DMA_ERROR (0x1) +#define FW_CFG_DMA_READ (0x2) +#define FW_CFG_DMA_SKIP (0x4) +#define FW_CFG_DMA_SELECT (0x8) + +struct fw_cfg_file { + uint32_t size; + uint16_t select; + uint16_t reserved; + char name[FW_CFG_MAX_FILE_PATH]; +}; + +struct fw_cfg_files { + __be32 count; + struct fw_cfg_file files[]; +}; + +struct fw_cfg_dma_access { + __be32 control; + __be32 length; + __be64 address; +}; + +void qemu_fwcfg_init(void); +uint16_t qemu_fwcfg_online_cpus(void); + +#endif diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 84fb082..c0a79d2 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -11,6 +11,7 @@ #include #include #include +#include "fw_cfg.h" static bool i440fx; @@ -57,6 +58,8 @@ static void qemu_chipset_init(void) x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, CONFIG_PCIE_ECAM_BASE | BAR_EN); } + + qemu_fwcfg_init(); } int arch_cpu_init(void)