| Message ID | 1450775889-16401-1-git-send-email-shengjiangwu@icloud.com |
|---|---|
| State | Accepted |
| Delegated to: | Marek Vasut |
| Headers | show |
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote: > Updated pinmux group MIXED1IO[15-20] for QSPI. > Updated QSPI clock. > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> > Cc: Chin Liang See <clsee@altera.com> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Dinh Nguyen <dinh.linux@gmail.com> > Cc: Pavel Machek <pavel@denx.de> > Cc: Marek Vasut <marex@denx.de> > Cc: Stefan Roese <sr@denx.de> Applied, thanks. I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks [1] http://git.denx.de/?p=u-boot/u-boot- socfpga.git;a=shortlog;h=refs/heads/master Best regards, Marek Vasut
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote: > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote: > > Updated pinmux group MIXED1IO[15-20] for QSPI. > > Updated QSPI clock. > > > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> > > Cc: Chin Liang See <clsee@altera.com> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > Cc: Dinh Nguyen <dinh.linux@gmail.com> > > Cc: Pavel Machek <pavel@denx.de> > > Cc: Marek Vasut <marex@denx.de> > > Cc: Stefan Roese <sr@denx.de> > > Applied, thanks. > > I will push your patches to [1] in a few hours, can you try and see if the > CV SOCDK works fine for you? Thanks > > [1] http://git.denx.de/?p=u-boot/u-boot- > socfpga.git;a=shortlog;h=refs/heads/master Pushed. Please let me know how SoCDK works for you now and if there are still some problems. Best regards, Marek Vasut
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0..06783dc 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 9e336e3..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------ board/altera/cyclone5-socdk/qts/pll_config.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-)